140dB Range (1nA to 10mA)
SGM834A
Logarithmic Current-to-Voltage Converter
DETAILED DESCRIPTION (continued)
Available Output Range
The low margin for the VLOG output for proper
trimming and cancellation is limited (0.1V, TYP). So,
when the actual input is very close to the intercept point
(IZ = 100pA), the output is saturated to the low limit
because VLOG cannot reach to zero. However, from
almost a decade higher (1nA), the output is valid. The
VLOG output impedance is 5kΩ. The adaptive biasing
and compensation block are fully functional over the
whole 3V to 5.5V supply range that helps in lowering
the errors caused by diode resistive drops that could
limit the effective high output range. The buffer amplifier
PPK (dB) power peak, results in a realistic PPK - 3dB
average power if the signal is averaged before
conversion. However, if the converter output is
averaged, the result will be a meaningless average
value of PPK/2 (dB) and also depends on 0dB
reference.
Bandwidth and Noise
Even though the AC transfer function is meaningless
for the nonlinear conversion circuit, the bandwidth data
can help the evaluation of the output settling time. This
is an important factor for reading and sampling the
output with high accuracy and fast rate. The Q1 acts as
a feedback path in the trans-impedance amplifier (TIA)
conversion (IPD to VBE). With low IPD values, the
trans-conductance (trans-linear) is very high and the
loop gain is low that limits the bandwidth. It means the
settling time will be long at low currents and short at
higher currents due to the large variation of the loop
gain. The bandwidth of TIA and the compensation
network are both increased when the IPD current goes
high. It is necessary to stabilize the loop gain and the
bandwidth. To this end, the external R1-C1 network is
shunted with the Q1. This will reduce the low current
bandwidth even further. By using the buffer amplifier,
the large bandwidth at higher currents is also limited by
the buffer bandwidth.
provides
a
much smaller (0.1Ω, TYP) output
impedance. With a 1kΩ load, this output can swing up
to VP - 0.1V. If the output is near VP - 0.1V, the law
conformance might have been lost already, because it
shows that the input current is above the guaranteed
operating range.
DC and AC Components
The logarithmic conversion is valid for the steady state
(settled DC) component of the input signal. The high
frequency AC component of the IPD should be filtered
and blocked from entering into the INPT pin. Otherwise,
large measurement errors are expected. Compared to
the averaging before conversion, the signal averaging
at the output of the converter adds much more error.
For example, a 50% duty cycle input pulse signal with
SG Micro Corp
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FEBRUARY 2022
14
SGMICRO [ Shengbang Microelectronics Co, Ltd ]
