SC4607
POWER MANAGEMENT
Application Information
Enable:
then connected to the junction of the external timing
capacitor and the added resistor as shown in Figure 1.
The SC4607 is enabled by applying a voltage greater than
2.25 volts to the VCC pin. The SC4607 is disabled when
VCC falls below 1.95 volts or when sleep mode opera-
tion is invoked by clamping the FS/SYNC pin to a voltage
below 75mV. 10µA is the typical current drawn through
the VCC pin during sleep mode. During the sleep mode,
the high side and low side MOSFETs are turned off and
the internal soft start voltage is held low.
SC4607
FS/SYNC
Ctiming
External
Clock
Signal
Rsync
Oscillator:
100 ohm
The FS/SYNC pin is used to set the PWM oscillator fre-
quency through an external timing capacitor that is con-
nected from the FS/SYNC pin to the GND pin. The re-
sulting ramp waveform on the FS/SYNC pin is a triangle
at the PWM frequency with a peak voltage of 1.3V and a
valley voltage of 0.3V. The PWM duty ratio is limited by
the ramp to a maximum of 97%, which allows the boot-
strap capacitor to be charged during each cycle. The ca-
pacitor tolerance adds to the accuracy of the oscillator
frequency. The approximate operating frequency and soft
start time are both determined by the value of the exter-
nal timing capacitor as shown in Table 1.
Figure 1
UVLO:
When the FS/SYNC pin is not pulled and held below 75mV,
the voltage on the Vcc pin determines the operation of
the SC4607. As Vcc increases during start up, the UVLO
block senses Vcc and keeps the high side and low side
MOSFETs off and the internal soft start voltage low until
Vcc reaches 2.25V. If no faults are present, the SC4607
will initiate a soft start when Vcc exceeds 2.25V. A hys-
teresis (100mV) in the UVLO comparator provides noise
immunity during its start up.
External Timing Frequency Soft Start Time (µs)
Capacitor Value
(pF)
(kHz)
Soft Start:
120
270
560
1000
580
628
The soft start function is required for step down control-
lers to prevent excess inrush current through the DC bus
during start up. Generally this can be done by sourcing a
controlled current into a timing capacitor and then using
the voltage across this capacitor to slowly ramp up the
error amp reference. The closed loop creates narrow
width driver pulses while the output voltage is low and
allows these pulses to increase to their steady state duty
cycle as the output voltage reaches its regulated value.
With this, the inrush current from the input side is con-
trolled. The duration of the soft start in the SC4607 is
controlled by an internal timing circuit which is used dur-
ing start up and over current to set the hiccup time. The
soft start time can be obtained from Table 1.
1220
1838
350
Table 1: Operating Frequency and Soft Start Time
Values Based On the Value of the External Timing
Capacitor Placed Across the FS/SYNC and GND Pins
Synchronous mode operation is invoked by using a sig-
nal from an external clock. A low value resistor (100Ω
typical) must be inserted in series with the timing capaci-
tor between the timing capacitor and the GND pin. The
other terminal of the timing capacitor will remain con-
nected to the FS/SYNC pin. The external clock signal is
The SC4607 implements its soft start by ramping up the
error amplifier reference voltage providing a controlled
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