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SC4607IMSTRT 参数 Datasheet PDF下载

SC4607IMSTRT图片预览
型号: SC4607IMSTRT
PDF下载: 下载PDF文件 查看货源
内容描述: 极低的输入,兆赫操作,高效率同步降压 [Very Low Input, MHz Operation, High Efficiency Synchronous Buck]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管信息通信管理
文件页数/大小: 17 页 / 319 K
品牌: SEMTECH [ SEMTECH CORPORATION ]
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SC4607  
POWER MANAGEMENT  
Pin Configuration  
Ordering Information  
Top View  
Part Number  
SC4607IMSTR  
SC4607IMSTRT(2)  
Device  
MSOP-10  
Notes:  
(1) Only available in tape and reel packaging. A reel  
contains 2500 devices.  
(2) Lead free product. This product is fully WEEE and  
RoHS compliant.  
(10 Pin MSOP)  
Pin Descriptions  
Pin #  
Pin Name  
Pin Function  
1
BST  
This pin enables the converter to drive an N-Channel high side MOSFET. BST connects to  
the external charge pump circuit. The charge pump circuit boosts the BST pin voltage to a  
sufficient gate-to-source voltage level for driving the gate of the high side MOSFET.  
2
3
VCC  
ISET  
Positive supply rail for the IC. For improved noise immunity, bypass this pin to GND with a  
0.1 to 4.7µF low ESL/ESR ceramic capacitor.  
The ISET pin is used to limit current in the high side MOSFET. The SC4607 uses the  
voltage across the Vin and ISET pins in order to set the current limit. The current limit  
threshold is set by the value of an external resistor (R3 in the Typical Application Circuit  
Diagram). Current limiting is performed by comparing the voltage drop across the sense  
resistor with the voltage drop across the drain to source resistance of the high side  
MOSFET during the MOSFET's conduction period. The voltage drop across the drain to  
source resistance of the high side MOSFET is obtained from the Vin and PHASE pins.  
4
5
COMP  
This is the output of the voltage amplifier. The voltage at this output is inverted internally and  
connected to the non-inverting input of the PWM comparator. A lead-lag network from the  
COMP pin to the VSENSE pin compensates for the two pole LC filter characteristics  
inherent to voltage mode control. The lead-lag network is required in order to optimize the  
dynamic performance of the voltage mode control loop.  
FS/SYNC  
The FS/SYNC pin sets the PWM oscillator frequency through an external timing capacitor  
that is connected from the FS/SYNC pin to the GND pin. Sleep mode operation is invoked  
by clamping the FS/SYNC pin to a voltage below 75mV. The typical supply current during  
sleep mode is 10µA. The SC4607 can be operated in synchronous mode by inserting a  
resistor in series between the timing capacitor and GND pin. The other terminal of the  
timing capacitor will remain connected to the FS/SYNC pin.  
6
7
VSENSE  
GND  
This pin is the inverting input of the voltage amplifier and serves as the output voltage  
feedback point for the Buck converter. VSENSE is compared to an internal reference value  
of 0.5V. VSENSE is hardwired to the output voltage when an output of 0.5V is desired.  
For higher output voltages, a resistor divider network is necessary (R7 and R9 in the Typical  
Application Circuit Diagram).  
Signal and power ground for the IC. All voltages are measured with respect to this pin. All  
bypass and timing capacitors connected to GND should have leads as short and direct as  
possible.  
2005 Semtech Corp.  
4
www.semtech.com