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SC4607IMSTRT 参数 Datasheet PDF下载

SC4607IMSTRT图片预览
型号: SC4607IMSTRT
PDF下载: 下载PDF文件 查看货源
内容描述: 极低的输入,兆赫操作,高效率同步降压 [Very Low Input, MHz Operation, High Efficiency Synchronous Buck]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管信息通信管理
文件页数/大小: 17 页 / 319 K
品牌: SEMTECH [ SEMTECH CORPORATION ]
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SC4607  
POWER MANAGEMENT  
Application Information (Cont.)  
voltage according to  
bottom MOSFET, its switching voltage is the body diode’s  
forward drop of the bottom MOSFET during its on/off  
transition. So the switching loss for the bottom MOSFET  
is negligible. Its total power loss can be determined by:  
R7  
R9  
Vout = 0.5 (1+  
)
PBOT _TOTAL = I2  
RBOT _ON + QGB VGATE fs +ID _AVG VF  
BST  
DRVH  
PHASE  
DRVL  
GND  
L1  
BOT _RMS  
Vout  
VCC  
ISET  
COMP  
Where:  
C9  
QGB = the total gate charge of the bottom MOSFET and  
VF = the forward voltage drop of the body diode of the  
bottom MOSFET.  
C1  
C2  
FS/SYNC VSENSE  
C4  
R
R7  
SC4607  
R8  
R1  
For a low voltage and high output current application such  
as the 3.3V/1.5V@12A case, the conduction loss is of-  
ten dominant and selecting low RDS(ON) MOSFETs will no-  
ticeably improve the efficiency of the converter even  
though they give higher switching losses.  
R9  
Figure 4. Compensation network provides 3  
poles and 2 zeros.  
Figure 5. Compensation network provides 3 poles and  
2 zeros.  
The gate charge loss portion of the top/bottom MOSFET’s  
total power loss is derived from the SC4607. This gate  
charge loss is based on certain operating conditions (fs,  
VGATE, and IO).  
For voltage mode step down applications as shown in  
Figure 5, the power stage transfer function is:  
s
The thermal estimations have to be done for both  
MOSFETs to make sure that their junction temperatures  
do not exceed their thermal ratings according to their  
total power losses PTOTAL, ambient temperature TA and their  
1+  
1
RC C4  
1+ s + s2L1C4  
GVD (s) = V  
I
L1  
R
thermal resistance R JA as follows:  
θ
Where:  
R = load resistance and  
RC = C4’s ESR.  
PTOTAL  
TJ(max) < TA +  
RθJA  
Loop Compensation Design:  
The compensation network will have the characteristic  
as follows:  
For a DC/DC converter, it is usually required that the  
converter has a loop gain of a high cross-over frequency  
for fast load response, high DC and low frequency gain  
for low steady state error, and enough phase margin for  
its operating stability. Often one can not have all these  
properties at the same time. The purpose of the loop  
compensation is to arrange the poles and zeros of the  
compensation network to meet the requirements for a  
specific application.  
s
ωZ1  
s
s
ωZ2  
s
1+  
1+  
1+  
1+  
ωI  
GCOMP (s) =  
s
ωP1  
ωP2  
Where  
1
ωI =  
R7 (C1 + C2 )  
The SC4607 has an internal error amplifier and requires  
the compensation network to connect among the COMP  
pin and VSNSE pin, GND, and the output as shown in  
Figure 5. The compensation network includes C1, C2,  
R1, R7, R8 and C9. R9 is used to program the output  
1
ωZ1  
=
R1 C2  
1
ωZ2  
=
(R7 + R8 ) C9  
2005 Semtech Corp.  
12  
www.semtech.com  
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