LC89057W-VF4A-E
10 Description of Demodulation Function
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The demodulation function is set with RXOPR. An initial value is set to an operating status.
10.1 Clocks
10.1.1 PLL (LPF)
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The LC89057W-VF4A-E incorporates a VCO (Voltage Controlled Oscillator) that can be stopped with PLLOPR and
it synchronizes with sampling frequencies from 32kHz to 192kHz and with the data with transfer rate from 4MHz to
25MHz.
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The PLL lock frequency is selected with PLLSEL. For systems whose input data sampling frequency is 105kHz or
lower, the initial setting of 512fs is recommended. Since the initial output value of the system clock RMCK is set to
1/2 of PLLSEL, the RMCK output is 256fs when a PLL clock frequency is 512fs.
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For reception systems whose sampling frequency is higher than 105kHz, switch the PLL clock frequency to 256fs. If
the same initial output setting is applied, RMCK is 128fs. Then set with PRSEL[1:0] when necessary.
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When the PLL lock frequency is selected with PLLSEL after PLL is locked, unlock is generated. Accordingly,
PLLSEL must be set prior to bi-phase data input.
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LPF is a pin for PLL loop filter. Connect the following resistance and capacitances regardless of PLLSEL settings.
LPF
Clock
512fs
256fs
R0
C0
C1
220Ω
0.1μF
0.022μF
R0
C1
C0
Figure 10.1 Loop Filter Configuration
10.1.2 Demodulation function without using PLL (TMCK)
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The LC89057W-VF4A-E has a function that processes input bi-phase data using an external clock (external clock
synchronization function). In normal demodulation processing, the built-in PLL generates a clock that is synchronized
with data and carries out data processing with the clock. In the LC89057W-VF4A-E, data processing can be also done
by providing a clock synchronized with data instead of the PLL-generated clock via an independent transmission path.
To use the external clock synchronization function, set the PLL unused demodulation function with EXSYNC, set the
256fs or 512fs clock with PLLSEL, and set 1/1 of PLLSEL set frequency with PRSEL[1:0]. After that input the clock
synchronized with input data to TMCK. By this settings, the same operation as PLL demodulation processing is
performed. For example, 512fs clock should be supplied with TMCK because the setting of PLLSEL is at 512fs in
case EXSYNC is set on initial condition. In the event of switching the setting of TMCK clock frequency to 256fs, the
setting of PLLSEL should be at 256fs.
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Jitter of input data and clock should be as small as possible. Excessive jitter might invite errors in operation of PLL.
Pay attention to the noise of clock transmission path.
In the external synchronization mode, supply clock with TMCK all the time. Without input of clock, system will shut
down and be in malfunction.
In case of using external clock synchronization mode only, it is not necessary to connect anything to LPF pin.
However, configuring PLL loop filter enables to use both PLL clock synchronization mode and external clock
synchronization mode by switching EXSYNC.
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Applying the external clock synchronization function can also configure a high-precision clock system using an
external PLL.
No.7202-13/59
SANYO [ SANYO SEMICON DEVICE ]
