LC72121, 72121M, 72121V
Structure of the Programmable Divider
DVS
SNS
Input pin
FMIN
Set divisor
272 to 65535
272 to 65535
4 to 4095
Actual divisor
Twice the set value
The set value
Input frequency range
10 to 160 MHz
2 to 40 MHz
A
B
C
1
0
0
*
1
0
AMIN
AMIN
The set value
0.5 to 10 MHz
*: Don’t care
Sample Programmable Divider Divisor Calculations
• For FM with a step size of 50 kHz (DVS = 1, SNS = *: FMIN selected)
FM RF = 90.0 MHz (IF +10.7 MHz)
FM VCO = 100.7 MHz
PLL fref = 25 kHz (R0 = 0, R1 = 1, R2 = 0, R3 = 0)
100.7 MHz (FM VCO) ÷ 25 kHz (fref) ÷ 2 (for the FMIN 1/2 prescaler) 2014 → 07DE (hexadecimal)
• For SW with a step size of 5 kHz (DVS = 0, SNS = 1: AMIN high-speed operation selected)
SW RF = 21.75 MHz (IF +450 kHz)
SW VCO = 22.20 MHz
PLL fref = 5 kHz (R0 = 0, R1 = 1, R2 = 0, R3 = 1)
22.2 MHz (SW VCO) ÷ 5 kHz (fref) = 4440 → 1158 (hexadecimal)
• For MW with a step size of 9 kHz (DVS = 0, SNS = 0: AMIN low-speed operation selected)
MW RF = 1008 kHz (IF +450 kHz)
WM VCO = 1458 kHz
PLL fref =9 kHz (R0 = 1, R1 = 0, R2 = 0, R3 = 1)
1458 (MW VCO) ÷ 9 kHz (fref) = 162 → 0A2 (hexadecimal)
No. 5815-14/22
SANYO [ SANYO SEMICON DEVICE ]
