S524A40X11/40X21/40X41/60X81/60X51 SERIAL EEPROM
DATA SHEET
SDA
WP
Start/Stop
Logic
HV Generation
Timing Control
Control Logic
EEPROM
Cell Array
128 x 8 bits
256 x 8 bits
512 x 8 bits
1024 x 8 bits
2048 x 8 bits
SCL
Slave Address
Comparator
Word Address
Pointer
Row
decoder
A0
A1
A2
Column Decoder
Data Register
DOUT and ACK
Figure 1-1. S524A40X11/40X21/40X41/60X81/60X51 Block Diagram
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