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S3C6410X66-YB40
S3C6410X_UM_REV0.00
PRODUCT OVERVIEW
1.1.3 MEMORY SUBSYSTEM
The S3C6410X microprocessor provides the following Memory Subsystem features:
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•
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High bandwidth Memory Matrix subsystem
Two independent external memory ports (1 SROM port and 1 DRAM ports)
Matrix architecture increases overall bandwidth with the simultaneous access capability
1.1.3.1 SROM Memory Port configurable to support the following memory types:
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Support SRAM/ROM/NOR Flash Interface
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−
x8 or x16 data bus
Address range support: max. 26-bit (128MB)
Muxed OneNAND Flash interface
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−
x16 data bus
Support muxed type OneNAND.
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NAND Flash Boot Loader
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System can be booted from NAND when system initialization begins
Supports both SLC and MLC NAND Flash memory
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CF interface
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Compatible with CF+ and CompactFlash Spec (Rev 3.0)
SDRAM Interface
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−
−
x16 data bus for Memory Port0
1.8/ 2.5V/3.3V interface voltage
Density support:
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Memory Port0: up to 1Gb
•Mobile SDRAM Interface
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−
−
−
−
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x16 data bus with 133Mbps/pin data rate for Memory Port0
133MHz address and command bus speed
1.8/ 2.5V/3.3V interface voltage for Memory Port0
1.8/ 2.5V interface voltage for Memory Port1
Density support: up to 1Gb
Mobile SDRAM feature support:
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∗
∗
DS (Driver Strength Control)
TCSR (Temperature Compensated Self-Refresh Control)
PASR (Partial Array Self-Refresh Control)
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Mobile DDR Interface
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−
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x16 data bus for Memory Port0, x32 data bus for Memory Port1
1.8/ 2.5V/3.3V interface voltage
Density support: up to 1Gb
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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SAMSUNG [ SAMSUNG ]
