Email:Tech@fosvos.com
HotTel:+86-21-58998693
S3C6410X66-YB40
S3C6410X_UM_REV0.00
PRODUCT OVERVIEW
PRODUCT OVERVIEW
1 ARCHITECTURAL OVERVIEW
The S3C6410X is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, low-power
capabilities, high performance Application Processor solution for mobile phones and general applications. To
provide optimized H/W performance for the 2.5G & 3G communication services, the S3C6410 adopts 64/32-bit
internal bus architecture. The 64/32-bit internal bus architecture is composed of AXI, AHB and APB buses. It also
includes many powerful hardware accelerators for tasks such as motion video processing, audio processing, 2D
graphics, display manipulation and scaling. An integrated Multi Format Codec (MFC) supports encoding and
decoding of MPEG4/H.263/H.264 and decoding of VC1. This H/W Encoder/Decoder supports real-time video
conferencing and TV out for both NTSC and PAL mode. Graphic 3D (hereinafter 3D Engine) is a 3D Graphics
Hardware Accelerator which can accelerate OpenGL ES 1.1 & 2.0 rendering. This 3D Engine includes two
programmable shaders: one vertex shader and one pixel shader.
The S3C6410 has an optimized interface to external memory. This optimized interface to external memory is
capable of sustaining the high memory bandwidths required in high-end communication services. The memory
system has dual external memory ports, DRAM and Flash/ROM/DRAM port. The DRAM port can be configured to
support mobile DDR, DDR, mobile SDRAM and SDRAM. The Flash/ROM/DRAM port supports NOR-Flash,
NAND-Flash, OneNAND, CF, ROM type external memory and mobile DDR, DDR, mobile SDRAM and SDRAM.
To reduce total system cost and enhance overall functionality, the S3C6410 includes many hardware peripherals
such as a Camera Interface, TFT 24-bit true color LCD controller, System Manager (power management & etc.),
4-channel UART, 32-channel DMA, 4-channel Timers, General Purpose I/O Ports, I2S-Bus interface, I2C-BUS
interface, USB Host, USB OTG Device operating at high speed (480Mbps), 3-channel SD/MMC Host Controller
and PLLs for clock generation.
The ARM subsystem is based on the ARM1176JZF-S core. It includes separate 16KB Instruction and 16KB data
caches, 16KB Instruction and 16KB Data TCM. It also includes a full MMU to handle virtual memory management.
The ARM1176JZF-S is a single chip MCU, which includes support for JAVA acceleration. The ARM1176JZF-S
includes a dedicated vector floating point coprocessor allowing efficient implementation of various encryption
schemes as well as high quality 3D graphics applications. The S3C6410X adopts the de-facto standard AMBA
bus architecture. These powerful, industry standard features allow the S3C6410X to support many of the industry
standard Operating Systems.
By providing a complete set of common system peripherals, the S3C6410X minimizes overall system costs and
eliminates the need to configure additional components. The S3C6410X is implemented using an advanced 90nm
CMOS process. The low-power, simple, elegant and fully static-design scheme is particularly suitable for cost-
sensitive and power-sensitive applications.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-1
SAMSUNG [ SAMSUNG ]
