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S3C6410X_UM_REV0.00
S3C6410X66-YB40
PRODUCT OVERVIEW
1.1.2 MICROPROCESSOR
The ARM1176JZF-S processor incorporates an integer unit that implements the ARM11 ARM architecture v6. It
supports the ARM, Thumb™ instruction sets and Jazelle technology to enable direct execution of Java bytecodes,
and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
The features of ARM1176JZF-S processor include:
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High-speed Advanced Microprocessor Bus Architecture (AMBA) Advanced Extensible Interface (AXI) level
two interfaces supporting prioritized multiprocessor implementations.
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Integer unit with integral EmbeddedICE-RT logic.
Eight-stage pipeline.
Branch prediction with return stack.
Low interrupt latency configuration.
coprocessors CP14 and CP15.
Instruction and Data Memory Management Units (MMUs), managed using MicroTLB structures backed by a
unified Main TLB.
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Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss (HUM).
Virtually indexed and physically addressed caches.
64-bit interface to both caches.
Vector Floating-Point (VFP) coprocessor support.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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SAMSUNG [ SAMSUNG ]
