INSTRUCTION SET
S3C4510B
INSTRUCTION SUMMARY
Table 3-1. The ARM Instruction Set
Instruction
Mnemonic
Action
ADC
ADD
AND
B
Add with carry
Rd: = Rn + Op2 + Carry
Rd: = Rn + Op2
Add
AND
Rd: = Rn AND Op2
R15: = address
Branch
BIC
BL
Bit clear
Rd: = Rn AND NOT Op2
R14: = R15, R15: = address
R15: = Rn,
Branch with link
Branch and exchange
BX
T bit: = Rn[0]
CDP
CMN
CMP
EOR
Coprocessor data processing
Compare negative
Compare
(coprocessor-specific)
CPSR flags: = Rn + Op2
CPSR flags: = Rn - Op2
Rd: = (Rn AND NOT Op2)
OR (op2 AND NOT Rn)
Coprocessor load
Exclusive OR
LDC
LDM
LDR
MCR
MLA
MOV
MRC
MRS
MSR
MUL
MVN
Load coprocessor from memory
Load multiple registers
Stack manipulation (Pop)
Rd: = (address)
Load register from memory
Move CPU register to coprocessor register
Multiply accumulate
cRn: = rRn {<op>cRm}
Rd: = (Rm * Rs) + Rn
Rd: = Op2
Move register or constant
Move from coprocessor register to CPU register Rn: = cRn {<op>cRm}
Move PSR status/flags to register
Move register to PSR status/flags
Multiply
Rn: = PSR
PSR: = Rm
Rd: = Rm * Rs
Move negative register
Rd: = 0xFFFFFFFF EOR Op2
3-2
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