S3C4510B
INSTRUCTION SET
3
INSTRUCTION SET
INSTRUCTION SET SUMMAY
This chapter describes the ARM instruction set and the THUMB instruction set in the ARM7TDMI core.
FORMAT SUMMARY
The ARM instruction set formats are shown below.
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8
7
6
5
4
3
2 1 0
Data processing/
PSR Transfer
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
Cond
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
Opcode
S
S
S
0
Rn
Rd
Rd
Rn
Operand2
0
0
0
1
0
U
B
0
A
A
0
1
Rs
Rn
1
1
1
0
1
1
0
0
0
0
S
S
0
0
1
1
1
1
1
1
Rm
Multiply
RdHi
Rn
RnLo
Rd
Rm
Rm
Multiply Long
1
0
0
1
0
0
0
1
0
0
1
0
0
Single data swap
Branch and exchange
1
0
0
1
1
1
1
1
1
1
1
1
0
0
Rn
Halfword data transfer:
register offset
Halfword data transfer:
immediate offset
P
P
P
U
U
U
0
W L
W L
W L
Rn
Rd
H
H
Rm
1
Rn
Rn
Rd
Rd
Offset
Offset
B
Offset
Single data transfer
Undefined
1
P
L
P
0
0
1
U
S
W L
W L
Rn
Register List
Block data transfer
Branch
Offset
Coprocessor data
transfer
Coprocessor data
Operation
U
N
Rn
CRd
CRd
Rd
CP#
Offset
CP Opc
CP Opc
CRn
CRn
CP#
CP#
CP#
CP#
0
1
CRm
CRm
Coprocessor register
Transfer
L
Ignored by processor
Software Interrupt
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8
7
6
5
4
3
2 1 0
Figure 3-1. ARM Instruction Set Format
NOTE
Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for
instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their
action may change in future ARM implementations.
3-1
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