S3C4510B
INTERRUPT CONTROLLER
13 INTERRUPT CONTROLLER
OVERVIEW
The S3C4510B interrupt controller has a total of 21 interrupt sources. Interrupt requests can be generated by
internal function blocks and at external pins.
The ARM7TDMI core recognizes two kinds of interrupts: a normal interrupt request (IRQ), and a fast interrupt
request (FIQ). Therefore all S3C4510B interrupts can be categorized as either IRQ or FIQ. The S3C4510B
interrupt controller has an interrupt pending bit for each interrupt source.
Four special registers are used to control interrupt generation and handling:
— Interrupt priority registers. The index number of each interrupt source is written to the pre-defined interrupt
priority register field to obtain that priority. The interrupt priorities are pre-defined from 0 to 20.
— Interrupt mode register. Defines the interrupt mode, IRQ or FIQ, for each interrupt source.
— Interrupt pending register. Indicates that an interrupt request is pending. If the pending bit is set, the interrupt
pending status is maintained until the CPU clears it by writing a "1" to the appropriate pending register. When
the pending bit is set, the interrupt service routine starts whenever the interrupt mask register is "0". The
service routine must clear the pending condition by writing a "1" to the appropriate pending bit. This avoids
the possibility of continuous interrupt requests from the same interrupt pending bit.
— Interrupt mask register. Indicates that the current interrupt has been disabled if the corresponding mask
bit is "1". If an interrupt mask bit is "0" the interrupt will be serviced normally. If the global mask bit (bit 21) is
set to "1", no interrupts are serviced. However, the source's pending bit is set if the interrupt is generated.
When the global mask bit has been set to "0", the interrupt is serviced.
13-1
SAMSUNG [ SAMSUNG ]
