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S3C4510B 参数 Datasheet PDF下载

S3C4510B图片预览
型号: S3C4510B
PDF下载: 下载PDF文件 查看货源
内容描述: 三星S3C4510B的16位/ 32位RISC微控制器是一款高性价比,高性能的基于以太网的系统微控制器解决方案。 [Samsungs S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller solution for Ethernet-based systems.]
分类和应用: 微控制器以太网
文件页数/大小: 422 页 / 2160 K
品牌: SAMSUNG [ SAMSUNG ]
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S3C4510B  
I C BUS CONTROLLER  
DATA TRSANSFER OPERATIONS  
Data Byte Format  
Every data byte that is put on the SDA line must be 8 bits long. The number of bytes that can be transmitted per  
transfer is unlimited. Each byte must be followed by an acknowledge bit. Data is transferred MSB-first.  
If the receiver cannot receive another complete byte of data until it has performed some other function (such as  
servicing an internal interrupt), it can hold the clock line SCL Low to force the transmitter into a wait state. The  
data transfer then continues when the receiver is ready for another byte of data and releases the SCL line.  
Acknowledge Procedure  
Data transfer with acknowledge is obligatory. The acknowledge-related clock pulses must be generated by the  
bus master. The transmitter releases the SDA line (High) during the acknowledge clock pulse.  
The receiver must pull down the SDA line during the acknowledge pulse so that it remains stable low during the  
High period of this clock pulse.  
Usually, a receiver which has been addressed is obliged to generate an acknowledge after each byte is received.  
When a slave receiver does not acknowledge from the slave address, the slave must leave the data line high.  
The master can then generate a stop condition to abort the transfer.  
If a slave receiver acknowledges the slave address, but later in the transfer cannot receive any more data bytes,  
the master must again abort the transfer. This is indicated by the slave not generating the acknowledge on the  
first byte to follow. The slave leaves the data line high and the master generates the stop condition.  
If a master receiver is involved in a transfer, it must signal the end of data to the slave transmitter by not  
generating an acknowledge on the last byte that was clocked out of the slave. The slave transmitter must then  
release the data line to let the master generate the stop condition.  
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