2
S3C4510B
I C BUS CONTROLLER
2
6
I C BUS CONTROLLER
OVERVIEW
The S3C4510B's internal IC bus (I2C-bus) controller has the following important features:
—
It requires only two bus lines, a serial data line (SDA) and a serial clock line (SCL). When the I2C-bus is free,
both lines are High level.
— Each device that is connected to the bus is software-addressable by a single master using a unique address.
slave relationships on the bus are constant. The bus master can be either a master-transmitter or a master-
receiver. The I2C bus controller supports only single master mode.
— It supports 8-bit, bi-directional, serial data transfers.
— The number of ICs that you can connect to the same I2C-bus is limited only by the maximum bus
capacitance of 400 pF.
Figure 6-1 shows a block diagram of the S3C4510B I2C-bus controller
Data
Control
Shift Buffer Register (IICBUF)
System Clock (fMCK)
SDA
SCL
Serial
Clock
Prescaler
SCL
Control 0
16
Prescaler Register (IICPS)
0
BUSY COND1 COND0
ACK
LRB
IEN
BF
Control Status Register (IICCON)
Figure 6-1. I2C BUS Block Diagram
6-1
SAMSUNG [ SAMSUNG ]
