2
I C BUS CONTROLLER
S3C4510B
I2C BUS SPECIAL REGISTERS
The I2C-bus controller has three special registers: a control status register (IICCON), a prescaler register (IICPS),
and a shift buffer register (IICBUF).
Control Status Register (IICCON)
The control status register for the I2C-bus, IICCON, is described in Table 6-2.
Table 6-1. Control Status Register (IICCON)
Register
Offset Address
R/W
Description
Control status register
Rest Value
IICCON
0xf000
R/W
0x00000000
Table 6-2. IICCON Register Description
Bit Number
Bit Name
Description
[0]
Buffer flag (BF)
The BF bit is set when the buffer is empty in transmit mode or
when the buffer is full in receive mode. To clear the buffer, you
write a "0" to this bit. The BF bit is cleared automatically
whenever the IICBUF register is written or read. If you set BF bit
to one, the I2C -bus is stopped. To activate I2C-bus, you should
clear the BF bit to zero.
[1]
[2]
Interrupt enable (IEN)
Last received bit (LRB)
Setting the interrupt enable bit to "1" enables the I2C-bus
interrupt.
The LRB bit is read only. It holds the value of the last received bit
over the I2C-bus. Normally, this bit will be the value of the slave
acknowledgement. To check for slave acknowledgement, you
test the LRB.
[3]
Acknowledge enable
(ACK)
The ACK bit is normally set to "1". This causes the I2C-bus
controller to send an acknowledge automatically after each byte.
This bit must be "0" when the I2C-bus controller is operating in
receiver mode and requires no further data to be received from
the slave transmitter. This causes a negative acknowledge on the
I2C-bus, which halts further reception from the slave device.
[5:4]
[6]
COND1, COND0
Bus busy (BUSY)
These bits control the generation of the start, Stop, and repeat
Start conditions: "00" = no effect, "01" = start, "10" = stop, and
"11" = repeat start.
This bit is a read-only flag that indicates when the I2C-bus is in
use. A "1" indicates that the bus is busy. This bit is set or cleared
by a start or stop condition, respectively.
[7]
Reset
If "1" is written to the reset bit, the I2C-bus controller is reset to its
initial state.
[31:8]
Reserved
Not applicable.
6-8
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