S3C4510B
UNIFIED INSTRUCTION/DATA CACHE
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UNIFIED INSTRUCTION/DATA CACHE
OVERVIEW
The S3C4510B CPU has a unified internal 8K byte instruction/data cache. Using cache control register settings,
you can use part or all of this cache as internal SRAM. To raise the cache hit ratio, the cache is configured using
two-way, set-associative addressing. The replacement algorithm is pseudo-LRU (Least Recently Used).
The cache line size is four words (16 bytes). When a miss occurs, four words must be fetched consecutively from
external memory. Typically, RISC processors take advantage of unified instruction/data caches to improve
performance. Without an instruction cache, bottlenecks that occur during instruction fetches from external
memory may seriously degrade performance.
CACHE CONFIGURATION
The S3C4510B’s 4K byte, two-way set-associative instruction/data cache uses a 15-bit tag address for each set.
The CS bits (a 2-bit value) in tag memory stores information for cache replacement. When a reset occurs, the CS
value is "00", indicating that the contents of cache set 0 and cache set 1 are invalid. When the first cache fill
operation occurs while exiting from the reset operation, the CS value becomes "01" at the specified line to
indicate that only set 0 is valid. When the subsequent cache fill occurs, the CS value becomes "11" at the
specified line, indicating that the contents of both set 0 and set 1 are valid.
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