SYSTEM MANAGER
S3C4510B
31 30 29 28 27
25 24
22 21
19 18
16 15 14 13 12 11
9
8
6
5
3
2
0
EXTACON0
EXTACON1
0
0
0
0
0
0
0
0
tACC1
tACC3
tCOH1
tCOH3
tACS1
tACS3
tCOS1
tCOS3
0
0
0
0
0
0
0
0
tACC0
tACC2
tCOH0
tCOH2
tACS0
tACS2
tCOS0
tCOS2
[2:0] Chip selection set-up time on nOE (tCOS0, tCOS2)
[18:16] tCOS1, tCOS3
000 = 0 cycle
001 = 1 cycle
010 = 2 cycles
011 = 3 cycles
100 = 4 cycles
101 = 5 cycles
110 = 6 cycles
111 = 7 cycles
[5:3] Address set-up time before nECS (tACS0, tACS2)
[21:19] tACS1, tACS3
000 = 0 cycle
001 = 1 cycle
010 = 2 cycles
011 = 3 cycles
100 = 4 cycles
101 = 5 cycle
110 = 6 cycle
111 = 7 cycles
[8:6] Chip selection hold time on nOE (tCOH0, tCOH2)
[24:22] tCOH1, tCOH3
000 = 0 cycle
001 = 1 cycle
010 = 2 cycles
011 = 3 cycles
100 = 4 cycles
101 = 5 cycles
110 = 6 cycles
111 = 7 cycles
[11:9] Access cycles (nOE low time) (tACC0, tACC2)
[27:25] tACC1, tACC3
000 = 0 cycle
001 = 1 cycle
010 = 2 cycles
011 = 3 cycles
100 = 4 cycles
101 = 5 cycles
110 = 6 cycles
111 = 7 cycles
Figure 4-10. External I/O Access Control Registers (EXTACON0, EXTACON1)
4-26
SAMSUNG [ SAMSUNG ]
