S3C4510B
SYSTEM MANAGER
SCLK
MCLKO
nECS
tNECS
tCOH
tNECS
tACC
tACS
tNROE
tNROE
nOE
Address
Data
tCOS
tADDRd
Addr
Data
tWs
tWh
nEWAIT
Data Read Point
(tCOH = 1)
tACS = 1 (1 cycle)
tCOS = 1 (1 cycle)
tACC = 1 (2 cycles)
tCOH = 1 (1 cycle)
Figure 4-13. External I/O Read Timing with nEWAIT
The nEWAIT should be valid at the first SCLK falling edge after nOE active. In this case, tCOS and tCOH need
to have a minimum of one cycle, and by the setting of tCOS value slower device can be supported. Naimly,
nEWAIT valid time depends on tCOS value. Deassertion timing depends on the applied Ext. I/O devices.
When the nEWAIT de-assert, it must be synchronized with MCLKO rising edge.(Because we can not detect
SCLK falling edge.) If not, memory state machine can go into the wrong state.
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