512MB, 1GB, 2GB Registered DIMMs
DDR2 SDRAM
DDR2 Registered DIMM Ordering Information
Part Number
Density Organization
Component Composition
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*9EA
64Mx8(K4T51083QC)*18EA
64Mx8(K4T51083QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*18EA
128Mx4(K4T51043QC)*36EA
128Mx4(K4T51043QC)*36EA
Number of Rank Parity Register
Height
30mm
30mm
30mm
30mm
30mm
30mm
30mm
30mm
M393T6553CZ3-CD5/CC
512MB
512MB
1GB
64Mx72
64Mx72
1
1
2
2
1
1
2
2
X
O
X
O
X
O
X
O
M393T6553CZA-CE7/E6/D5/CC
M393T2953CZ3-CD5/CC
128Mx72
128Mx72
128Mx72
128Mx72
256Mx72
256Mx72
M393T2953CZA-CE7/E6/D5/CC
M393T2950CZ3-CD5/CC
1GB
1GB
M393T2950CZA-CE7/E6/D5/CC
M393T5750CZ3-CD5/CC
1GB
2GB
M393T5750CZA-CE7/E6/D5/CC
2GB
Note: “Z” of Part number(11th digit) stand for Lead-free products.
Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.
Note: "A" of Part number(12th digit) stand for Parity Register products.
Features
•
Performance range
E7(DDR2-800)
E6(DDR2-667)
D5(DDR2-533)
CC(DDR2-400)
Unit
Mbps
Mbps
Mbps
CK
Speed@CL3
Speed@CL4
Speed@CL5
CL-tRCD-tRP
400
533
400
533
400
533
-
400
400
-
800
667
5-5-5
5-5-5
4-4-4
3-3-3
•
•
JEDEC standard 1.8V ± 0.1V Power Supply
= 1.8V ± 0.1V
V
DDQ
•
200 MHz f for 400Mb/sec/pin, 267MHz f for 533Mb/sec/pin, 333MHz f for 667Mb/sec/pin, 400MHz f for 800Mb/sec/pin
CK CK CK CK
•
•
•
•
•
•
•
4 Banks
Posted CAS
Programmable CAS Latency: 3, 4, 5
Programmable Additive Latency: 0, 1 , 2 , 3 and 4
Write Latency(WL) = Read Latency(RL) -1
Burst Length: 4 , 8(Interleave/nibble sequential)
Programmable Sequential / Interleave Burst Mode
•
•
•
•
•
Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
Off-Chip Driver(OCD) Impedance Adjustment
On Die Termination with selectable values(50/75/150 ohms or disable)
PASR(Partial Array Self Refresh)
Average Refresh Period 7.8us at lower than a T
85°C, 3.9us at 85°C < T
< 95 °C
CASE
CASE
- support High Temperature Self-Refresh rate enable feature
•
•
Serial presence detect with EEPROM
DDR2 SDRAM Package: 60ball FBGA - 128Mx4/64Mx8
•
All of Lead-free products are compliant for RoHS
Note: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram.
Address Configuration
Organization
Row Address
A0-A13
Column Address
A0-A9,A11
A0-A9
Bank Address
BA0-BA1
Auto Precharge
128Mx4(512Mb) based Module
64Mx8(512Mb) based Module
A10
A10
A0-A13
BA0-BA1
Rev. 1.2 Aug. 2005
SAMSUNG [ SAMSUNG ]
