K9F5608U0B-VCB0,VIB0,FCB0,FIB0
K9F5608Q0B-DCB0,DIB0,HCB0,HIB0
K9F5608U0B-YCB0,YIB0,PCB0,PIB0
K9F5608U0B-DCB0,DIB0,HCB0,HIB0
K9F5616Q0B-DCB0,DIB0,HCB0,HIB0
K9F5616U0B-YCB0,YIB0,PCB0,PIB0
K9F5616U0B-DCB0,DIB0,HCB0,HIB0
FLASH MEMORY
VALID BLOCK
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
NVB
2013
-
2048
Blocks
NOTE :
1. The K9F56XXX0B may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks
is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or
program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3. The number of initial bad blocks upon shipping does not exceed 20.
4. Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
AC TEST CONDITION
(K9F56XXX0B-XCB0 :TA=0 to 70°C, K9F56XXX0B-XIB0 :TA=-40 to 85°C
K9F56XXQ0B : Vcc=1.70V~1.95V , K9F56XXU0B : Vcc=2.7V~3.6V unless otherwise noted)
Parameter
K9F56XXQ0B
0V to VccQ
5ns
K9F56XXU0B
0.4V to 2.4V
5ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
VccQ/2
1.5V
K9F56XXQ0B:Output Load (VccQ:1.8V +/-10%)
K9F56XXU0B:Output Load (VccQ:3.0V +/-10%)
1 TTL GATE and CL=30pF
-
1 TTL GATE and CL=50pF
1 TTL GATE and CL=100pF
K9F56XXU0B:Output Load (VccQ:3.3V +/-10%)
CAPACITANCE(TA=25°C, VCC=1.8V/3.3V, f=1.0MHz)
Item
Symbol
Test Condition
Min
Max
10
Unit
pF
Input/Output Capacitance
Input Capacitance
CI/O
VIL=0V
-
-
CIN
VIN=0V
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
H
L
ALE
L
CE
L
WE
RE
H
GND
WP
X
Mode
X
X
X
X
L
Command Input
Read Mode
H
L
L
H
X
Address Input(3clock)
Command Input
H
L
L
H
H
Write Mode
H
L
L
H
H
Address Input(3clock)
L
L
H
H
Data Input
Data Output
L
L
L
H
H
L
X
L
L
L
H
H
L
X
During Read(Busy) on K9F5608U0B_Y,P or K9F5608U0B_V,F
During Read(Busy) on the devices except K9F5608U0B_Y,P and
K9F5608U0B_V,F
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
H
X
X
X
X
X
X
X
X
L
X
H
During Program(Busy)
During Erase(Busy)
Write Protect
H
L
X(1)
X
X
(2)
0V
Stand-by
0V/VCC
NOTE : 1. X can be VIL or VIH.
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
500
2
Unit
ms
Program Time
tPROG
-
-
-
-
200
Main Array
-
-
cycles
cycles
ms
Number of Partial Program Cycles
in the Same Page
Nop
Spare Array
3
Block Erase Time
tBERS
2
3
12
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