K9F2808U0B-YCB0,YIB0
K9F2808Q0B-DCB0,DIB0
K9F2808U0B-VCB0,VIB0 K9F2808U0B-DCB0,DIB0
FLASH MEMORY
Figure 8-1. Sequential Row Read2 Operation (GND Input=Fixed Low)
(only for K9F2808U0B-Y and K9F2808U0B-V, valid within a block)
tR
tR
tR
R/B
Start Add.(3Cycle)
Data Output
1st
Data Output
I/O0~7
50h
Data Output
2nd
(16Byte)
Nth
(16Byte)
A0 ~ A3 & A9 ~ A24
(A4 ~ A7 :
Don¢t Care)
1st
Block
Nth
Data Field
Spare Field
PAGE PROGRAM
The device is programmed basically on a page basis, but it allows multiple partial page program of one byte or consecutive bytes up
to 528, in a single page program cycle. The number of consecutive partial page program operation within the same page without
intervening erase operation should not exceed 2 for main array and 3 for spare array. The addressing may be done in any random
order in a block. Page program cycle consists of a serial data loading(up to 528 bytes of data) into the page register, and prog ram of
loaded data into the appropriate cell. Serial data loading can start in 2nd half array by moving pointer. About the pointer operation,
please refer to the attached technical notes. Serial data loading is executed by entering the Serial Data Input command(80h) and
three cycle address input and then serial data loading. The bytes except those to be programmed need not to be loaded. The Page
Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering 80h will not initiate
program process. The internal write controller automatically executes the algorithms and timings necessary for program and verifica-
tion, thereby freeing the CPU for other tasks. Once the program process starts, the Read Status Register command may be entered,
with RE and CE low, to read the status register. The CPU can detect the completion of a program cycle by monitoring the R/B out-
put, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming
is in progress. When the Page Program is completed, the Write Status Bit(I/O 0) may be checked(Figure 9). The internal write verifi-
cation detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status com-
mand mode until another valid command is written to the command register.
Figure 9 details the sequence.
Figure 9. Program & Read Status Operation
tPROG
R/B
Pass
I/O0~7
80h
Address & Data Input
I/O0
Fail
10h
70h
A0 ~ A7 & A9 ~ A23
528 Byte Data
25
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