欢迎访问ic37.com |
会员登录 免费注册
发布采购

K6T0808C1D-DL70 参数 Datasheet PDF下载

K6T0808C1D-DL70图片预览
型号: K6T0808C1D-DL70
PDF下载: 下载PDF文件 查看货源
内容描述: 32Kx8位低功耗CMOS静态RAM [32Kx8 bit Low Power CMOS Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 9 页 / 172 K
品牌: SAMSUNG [ SAMSUNG ]
 浏览型号K6T0808C1D-DL70的Datasheet PDF文件第1页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第2页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第3页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第4页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第5页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第6页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第8页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第9页  
K6T0808C1D Family  
CMOS SRAM  
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)  
tWC  
Address  
tCW(2)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tAS(3)  
tDW  
tDH  
Data Valid  
Data in  
tWHZ  
tOW  
Data Undefined  
Data out  
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)  
tWC  
Address  
tCW(2)  
tAS(3)  
tWR(4)  
CS  
tAW  
tWP(1)  
WE  
tDW  
tDH  
Data in  
Data Valid  
High-Z  
Data out  
High-Z  
NOTES (WRITE CYCLE)  
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE  
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write  
to the end of write.  
2. tCW is measured from the CS going low to end of write.  
3. tAS is measured from the address valid to the beginning of write.  
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.  
DATA RETENTION WAVE FORM  
CS controlled  
Data Retention Mode  
tSDR  
tRDR  
VCC  
4.5V  
2.2V  
VDR  
CS³ VCC - 0.2V  
CS  
GND  
Revision 1.0  
November 1997