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K6T0808C1D-DL70 参数 Datasheet PDF下载

K6T0808C1D-DL70图片预览
型号: K6T0808C1D-DL70
PDF下载: 下载PDF文件 查看货源
内容描述: 32Kx8位低功耗CMOS静态RAM [32Kx8 bit Low Power CMOS Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 9 页 / 172 K
品牌: SAMSUNG [ SAMSUNG ]
 浏览型号K6T0808C1D-DL70的Datasheet PDF文件第1页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第2页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第3页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第4页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第6页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第7页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第8页浏览型号K6T0808C1D-DL70的Datasheet PDF文件第9页  
K6T0808C1D Family  
CMOS SRAM  
AC OPERATING CONDITIONS  
TEST CONDITIONS (Test Load and Test Input/Output Reference)  
Input pulse level : 0.8 to 2.4V  
1)  
Input rising and falling time : 5ns  
CL  
Input and output reference voltage : 1.5V  
Output load (See right) :CL=100pF+1TTL  
CL=50pF+1TTL  
1. Including scope and jig capacitance  
AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T0808C1D-L Family:TA=0 to 70°C, K6T0808C1D-P Family:TA=-40 to 85°C)  
Speed Bins  
Parameter List  
Symbol  
Units  
551)ns  
Max  
70ns  
Min  
55  
-
Min  
70  
-
Max  
Read cycle time  
tRC  
tAA  
-
55  
55  
25  
-
-
70  
70  
35  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Address access time  
Chip select to output  
tCO  
tOE  
-
-
Output enable to valid output  
Chip select to low-Z output  
Output enable to low-Z output  
Chip disable to high-Z output  
Output disable to high-Z output  
Output hold from address change  
Write cycle time  
-
-
Read  
tLZ  
10  
5
10  
5
tOLZ  
tHZ  
-
-
0
20  
20  
-
0
30  
30  
-
tOHZ  
tOH  
tWC  
tCW  
tAS  
0
0
10  
55  
45  
0
10  
70  
60  
0
-
-
Chip select to end of write  
Address set-up time  
-
-
-
-
Address valid to end of write  
Write pulse width  
tAW  
tWP  
tWR  
tWHZ  
tDW  
tDH  
45  
40  
0
-
60  
50  
0
-
-
-
Write  
Write recovery time  
-
-
Write to output high-Z  
0
20  
-
0
25  
-
Data to write time overlap  
Data hold from write time  
End write to output low-Z  
25  
0
30  
0
-
-
tOW  
5
-
5
-
1. The parameter is tested with 50pF test load.  
DATA RETENTION CHARACTERISTICS  
Item  
Symbol  
Test Condition  
Min  
Typ  
Max  
5.5  
15  
3
Unit  
Vcc for data retention  
VDR  
CS³ Vcc-0.2V  
2.0  
-
-
1
V
L-Ver  
Data retention current  
IDR  
Vcc=3.0V, CS³ Vcc-0.2V  
mA  
LL-Ver  
-
0.2  
-
Data retention set-up time  
Recovery time  
tSDR  
tRDR  
0
-
See data retention waveform  
ms  
5
-
-
Revision 1.0  
November 1997