K4H560438E-GCCC 参数 Datasheet PDF下载

型号：	K4H560438E-GCCC
PDF下载：	下载PDF文件查看货源
内容描述：	256Mb的E-死DDR 400 SDRAM内存规格60Ball FBGA （ X4 / X8 ） [256Mb E-die DDR 400 SDRAM Specification 60Ball FBGA (x4/x8)]
分类和应用：	内存集成电路动态存储器双倍数据速率时钟
文件页数/大小：	18 页 / 199 K
品牌：	SAMSUNG [ SAMSUNG ]

DDR SDRAM 256Mb E-die (x4, x8)

DDR SDRAM

j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser

on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter

mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.

k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi

tions through the DC region must be monotony.

Rev. 1.1 September. 2003