64M DDR SDRAM
K4D64163HF
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
The differential system clock Input.
CK, CK*1
Input
Input
Input
All of the inputs are sampled on the rising edge of the clock except
DQ’s and DM’s that are sampled on both edges of the DQS.
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CKE
CS
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
RAS
CAS
WE
Input
Input
Input
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data Strobe : Output with read data, input with write data. Edge-
aligned with read data, centered in write data. Used to capture write
data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ;
UDQS corresponds to the data on DQ8-DQ15.
LDQS,(U)DQS
LDM,UDM
Input/Output
Input Data Mask : DM is an input mask signal for write data. Input
data is masked when DM is sampled HIGH along with that input data
during a WRITE access. DM is sampled on both edges of DQS. DM
pins include dummy loading internally, to matches the DQ and DQS
loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ;
UDM correspons to the data on DQ8-DQ15.
Input
DQ0 ~ DQ15
BA0, BA1
Input/Output
Input
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7.
A0 ~ A11
VDD/VSS
Input
Power Supply
Power Supply
Power Supply
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
VDDQ/VSSQ
VREF
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
This pin is recommended to be left "No connection" on the device
Reserved for future use
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 -
Rev. 1.1(Aug. 2002)
SAMSUNG [ SAMSUNG ]
