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K4D64163HF-TC33 参数 Datasheet PDF下载

K4D64163HF-TC33图片预览
型号: K4D64163HF-TC33
PDF下载: 下载PDF文件 查看货源
内容描述: 1米x 16Bit的×4银行双数据速率同步DRAM [1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM]
分类和应用: 内存集成电路光电二极管动态存储器双倍数据速率时钟
文件页数/大小: 16 页 / 164 K
品牌: SAMSUNG [ SAMSUNG ]
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64M DDR SDRAM  
K4D64163HF  
1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM  
with Bi-directional Data Strobe and DLL  
FEATURES  
• 3.3V + 5% power supply for device operation  
• 2.5V + 5% power supply for I/O interface  
• SSTL_2 compatible inputs/outputs  
• 4 banks operation  
• 2 DQS’s ( 1DQS / Byte )  
• Data I/O transactions on both edges of Data strobe  
• DLL aligns DQ and DQS transitions with Clock transition  
• Edge aligned data & data strobe output  
• Center aligned data & data strobe input  
• DM for write masking only  
• MRS cycle with address key programs  
-. Read latency 3 (clock)  
-. Burst length (2, 4 and 8)  
• Auto & Self refresh  
-. Burst type (sequential & interleave)  
• All inputs except data & DM are sampled at the positive  
going edge of the system clock  
• 64ms refresh period (4K cycle)  
• 66pin TSOP-II  
• Maximum clock frequency up to 300MHz  
• Maximum data rate up to 600Mbps/pin  
• Differential clock input  
• No Wrtie-Interrupted by Read Function  
ORDERING INFORMATION  
Part NO.  
Max Freq.  
300MHz  
275MHz  
250MHz  
200MHz  
166MHz  
Max Data Rate  
600Mbps/pin  
550Mbps/pin  
500Mbps/pin  
400Mbps/pin  
333Mbps/pin  
Interface  
Package  
K4D64163HF-TC33  
K4D64163HF-TC36  
K4D64163HF-TC40  
K4D64163HF-TC50  
K4D64163HF-TC60  
SSTL_2  
66 pin TSOP-II  
GENERAL DESCRIPTION  
FOR 1M x 16Bit x 4 Bank DDR SDRAM  
The K4D64163H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 16  
bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous features with Data Strobe allow  
extremely high performance up to 1.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of  
operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of  
high performance memory system applications.  
- 3 -  
Rev. 1.1(Aug. 2002)  
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