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    DS2154LA2+ 参数 Datasheet PDF下载

    DS2154LA2+图片预览
    型号： DS2154LA2+
    PDF下载： 下载PDF文件 查看货源
    内容描述： [DATACOM, FRAMER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, LQFP-100]
    分类和应用： 电信电信集成电路
    文件页数/大小： 90 页 / 1731 K
    品牌： ROCHESTER [ Rochester Electronics ]
     浏览型号DS2154LA2+的Datasheet PDF文件第1页浏览型号DS2154LA2+的Datasheet PDF文件第2页浏览型号DS2154LA2+的Datasheet PDF文件第4页浏览型号DS2154LA2+的Datasheet PDF文件第5页浏览型号DS2154LA2+的Datasheet PDF文件第6页浏览型号DS2154LA2+的Datasheet PDF文件第7页浏览型号DS2154LA2+的Datasheet PDF文件第8页浏览型号DS2154LA2+的Datasheet PDF文件第9页  
    DS2154
    TABLE OF CONTENTS
    1
    DETAILED DESCRIPTION....................................................................................................6
    1.1
    1.1.1
    I
    NTRODUCTION
    ............................................................................................................................. 6
    New Features......................................................................................................................................... 6
    1.2
    1.3
    F
    UNCTIONAL
    D
    ESCRIPTION
    ........................................................................................................... 7
    R
    EADER
    ’
    S
    N
    OTE
    ........................................................................................................................... 7
    T
    RANSMIT
    S
    IDE
    D
    IGITAL
    P
    INS
    ...................................................................................................... 11
    R
    ECEIVE
    S
    IDE
    D
    IGITAL
    P
    INS
    ........................................................................................................ 12
    P
    ARALLEL
    C
    ONTROL
    P
    ORT
    P
    INS
    ................................................................................................. 13
    L
    INE
    I
    NTERFACE
    P
    INS
    ................................................................................................................. 14
    S
    UPPLY
    P
    INS
    .............................................................................................................................. 14
    2
    PIN DESCRIPTION................................................................................................................9
    2.1
    2.2
    2.3
    2.4
    2.5
    3
    4
    PARALLEL PORT ...............................................................................................................20
    CONTROL, ID, AND TEST REGISTERS ............................................................................20
    4.1
    4.2
    4.3
    4.4
    4.5
    F
    RAMER
    L
    OOPBACK
    .................................................................................................................... 29
    L
    OCAL
    L
    OOPBACK
    ....................................................................................................................... 29
    R
    EMOTE
    L
    OOPBACK
    .................................................................................................................... 29
    P
    OWER
    -U
    P
    S
    EQUENCE
    ............................................................................................................... 30
    A
    UTOMATIC
    A
    LARM
    G
    ENERATION
    ................................................................................................ 30
    CRC4 S
    YNC
    C
    OUNTER
    ............................................................................................................... 33
    BPV
    OR
    C
    ODE
    V
    IOLATION
    C
    OUNTER
    ........................................................................................... 39
    CRC4 E
    RROR
    C
    OUNTER
    ............................................................................................................ 40
    E-B
    IT
    C
    OUNTER
    ......................................................................................................................... 40
    FAS E
    RROR
    C
    OUNTER
    ............................................................................................................... 41
    5
    6
    STATUS AND INFORMATION REGISTERS ......................................................................31
    5.1
    6.1
    6.2
    6.3
    6.4
    ERROR COUNT REGISTERS.............................................................................................39
    7
    8
    DS0 MONITORING FUNCTION ..........................................................................................42
    SIGNALING OPERATION...................................................................................................46
    8.1
    8.2
    8.2.1
    8.2.2
    P
    ROCESSOR
    -B
    ASED
    S
    IGNALING
    .................................................................................................. 46
    H
    ARDWARE
    -B
    ASED
    S
    IGNALING
    ................................................................................................... 49
    Receive Side ........................................................................................................................................ 49
    Transmit Side ....................................................................................................................................... 49
    9
    PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK .....................................51
    9.1
    9.1.1
    9.1.2
    T
    RANSMIT
    S
    IDE
    C
    ODE
    G
    ENERATION
    ............................................................................................ 51
    Simple Idle Code Insertion and Per-Channel Loopback...................................................................... 51
    Per-Channel Code Insertion ................................................................................................................ 52
    9.2
    R
    ECEIVE
    S
    IDE
    C
    ODE
    G
    ENERATION
    .............................................................................................. 53
    10
    11
    11.1
    11.2
    CLOCK BLOCKING REGISTERS..................................................................................55
    ELASTIC STORES OPERATION ...................................................................................57
    R
    ECEIVE
    S
    IDE
    ............................................................................................................................ 57
    T
    RANSMIT
    S
    IDE
    .......................................................................................................................... 57
    12
    12.1
    12.2
    12.3
    ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION................................58
    H
    ARDWARE
    S
    CHEME
    .................................................................................................................. 58
    I
    NTERNAL
    R
    EGISTER
    S
    CHEME
    B
    ASED ON
    D
    OUBLE
    -F
    RAME
    ........................................................... 58
    I
    NTERNAL
    R
    EGISTER
    S
    CHEME
    B
    ASED ON
    CRC4 M
    ULTIFRAME
    ..................................................... 61
    2 of 87

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