DS2154
4.4 Power-Up Sequence
On power-up, after the supplies are stable, the DS2154 should be configured for operation by writing to
all of the internal registers (this includes the Test Registers) since the contents of the internal registers
cannot be predicted on power-up. Next, the LIRST (CCR5.7) bit should be toggled from 0 to 1 to reset
the line interface circuitry (it will take the DS2154 about 40ms to recover from the LIRST bit being
toggled). Finally, after the RSYSCLK and TSYSCLK inputs are stable, the ESR bit should be toggled
from a 0 to a 1 and then back to 0 (this step can be skipped if the elastic stores are not being used). Both
TCLK and RCLKI must be present for the parallel control port to operate properly.
4.5 Automatic Alarm Generation
When either CCR2.4 or CCR2.5 is set to 1, the DS2154 monitors the receive side to determine if any of
the following conditions are present: loss of receive frame synchronization, AIS alarm (all 1s) reception,
or loss of receive carrier (or signal). If any one (or more) of the above conditions is present, then the
DS2154 will either force an AIS alarm (if CCR2.5 = 1) or a Remote Alarm (CCR2.4 = 1) to be
transmitted via the TPOSO and TNEGO pins. It is an illegal state to have both CCR2.4 and CCR2.5 set to
1 at the same time. If CCR2.4 = 1, then RAI will be transmitted according to ETS 300 011 specifications
and a constant Remote Alarm will be transmitted if the DS2154 cannot find CRC4 multiframe
synchronization within 400ms as per G.706.
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ROCHESTER [ Rochester Electronics ]
