ADSP-BF531/ADSP-BF532/ADSP-BF533
Timer Cycle Timing
Table 35 and Figure 30 describe timer expired operations. The
input signal is asynchronous in width capture mode and exter-
nal clock mode and has an absolute maximum input frequency
of fSCLK/2 MHz.
Table 35. Timer Cycle Timing
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Min
Max
Unit
Timing Characteristics
tWL Timer Pulse Width Input Low1 (Measured in SCLK Cycles)
tWH Timer Pulse Width Input High1 (Measured in SCLK Cycles)
Switching Characteristic
1
1
1
1
SCLK
SCLK
tHTO Timer Pulse Width Output2 (Measured in SCLK Cycles)
1
(232–1)
1
(232–1)
SCLK
1 The minimum pulse widths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.
2 The minimum time for tHTO is one cycle, and the maximum time for tHTO equals (232–1) cycles.
CLKOUT
tTOD
TMRx OUTPUT
tTIS
tTIH
tHTO
TMRx INPUT
tWH,tWL
Figure 30. Timer PWM_OUT Cycle Timing
Rev. H
| Page 42 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
