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ADSP-BF532SBBZ400 参数 Datasheet PDF下载

ADSP-BF532SBBZ400图片预览
型号: ADSP-BF532SBBZ400
PDF下载: 下载PDF文件 查看货源
内容描述: [16-BIT, 40 MHz, OTHER DSP, PBGA169, ROHS COMPLIANT, PLASTIC, MO-034AAG-2, BGA-169]
分类和应用: 时钟外围集成电路
文件页数/大小: 65 页 / 5323 K
品牌: ROCHESTER [ Rochester Electronics ]
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ADSP-BF531/ADSP-BF532/ADSP-BF533  
The time tDECAY is calculated with test loads CL and IL, and with  
V equal to 0.1 V for VDDEXT (nominal) = 1.8 V or 0.5 V for  
TEST CONDITIONS  
All timing parameters appearing in this data sheet were mea-  
sured under the conditions described in this section. Figure 44  
shows the measurement point for ac measurements (except out-  
put enable/disable). The measurement point VMEAS is 0.95 V for  
V
DDEXT (nominal) = 2.5 V/3.3 V.  
The time tDIS_MEASURED is the interval from when the reference  
signal switches, to when the output voltage decays V from the  
measured output high or output low voltage.  
V
DDEXT (nominal) = 1.8 V or 1.5 V for VDDEXT (nominal) = 2.5 V/  
3.3 V.  
REFERENCE  
SIGNAL  
INPUT  
OR  
OUTPUT  
V
V
MEAS  
MEAS  
tDIS_MEASURED  
tENA_MEASURED  
tDIS  
tENA  
V
OH  
V
(MEASURED)  
Figure 44. Voltage Reference Levels for AC  
Measurements (Except Output Enable/Disable)  
OH  
(MEASURED)  
V
(MEASURED) ؊ ⌬V  
(MEASURED) + V  
OH  
V
(HIGH)  
TRIP  
V
(LOW)  
V
V
TRIP  
OL  
V
OL  
(MEASURED)  
OL  
(MEASURED)  
Output Enable Time Measurement  
tDECAY  
tTRIP  
Output pins are considered to be enabled when they have made  
a transition from a high impedance state to the point when they  
start driving.  
The output enable time tENA is the interval from the point when  
a reference signal reaches a high or low voltage level to the point  
when the output starts driving as shown on the right side of  
Figure 45.  
OUTPUT STOPS DRIVING  
OUTPUT STARTS DRIVING  
HIGH IMPEDANCE STATE  
Figure 45. Output Enable/Disable  
Example System Hold Time Calculation  
The time tENA_MEASURED is the interval, from when the reference  
signal switches, to when the output voltage reaches VTRIP(high)  
or VTRIP (low).  
For VDDEXT (nominal) = 1.8 V—VTRIP (high) is 1.3 V and VTRIP  
(low) is 0.7 V.  
To determine the data output hold time in a particular system,  
first calculate tDECAY using the equation given above. Choose V  
to be the difference between the processor’s output voltage and  
the input threshold for the device requiring the hold time. CLis  
the total bus capacitance (per data line), and IL is the total leak-  
age or three-state current (per data line). The hold time is tDECAY  
plus the various output disable times as specified in the Timing  
Specifications on Page 28 (for example tDSDAT for an SDRAM  
write cycle as shown in SDRAM Interface Timing on Page 31).  
For VDDEXT (nominal) = 2.5 V/3.3 V—VTRIP (high) is 2.0 V and  
VTRIP (low) is 1.0 V.  
Time tTRIP is the interval from when the output starts driving to  
when the output reaches the VTRIP (high) or VTRIP (low) trip  
voltage.  
Time tENA is calculated as shown in the equation:  
tENA = tENA_MEASURED tTRIP  
If multiple pins (such as the data bus) are enabled, the measure-  
ment value is that of the first pin to start driving.  
Output Disable Time Measurement  
Output pins are considered to be disabled when they stop driv-  
ing, go into a high impedance state, and start to decay from their  
output high or low voltage. The output disable time tDIS is the  
difference between tDIS_MEASURED and tDECAY as shown on the left  
side of Figure 44.  
tDIS = tDIS_MEASURED tDECAY  
The time for the voltage on the bus to decay by V is dependent  
on the capacitive load CL and the load current II. This decay time  
can be approximated by the equation:  
tDECAY = CLV  IL  
Rev. H  
| Page 46 of 64 | January 2011  
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