ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 33. Serial Peripheral Interface (SPI) Port—Slave Timing
VDDEXT = 1.8 V
LQFP/PBGA Packages
VDDEXT = 1.8 V
CSP_BGA Package
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Timing Requirements
tSPICHS Serial Clock High Period
tSPICLS Serial Clock Low Period
tSPICLK Serial Clock Period
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
2 × tSCLK –1.5
2 × tSCLK –1.5
4 × tSCLK
ns
ns
ns
ns
ns
ns
ns
ns
tHDS
Last SCK Edge to SPISS Not Asserted
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
2 × tSCLK –1.5
2 × tSCLK –1.5
2 × tSCLK –1.5
1.6
tSPITDS Sequential Transfer Delay
tSDSCI SPISS Assertion to First SCK Edge
tSSPID Data Input Valid to SCK Edge (Data Input Setup) 1.6
tHSPID SCK Sampling Edge to Data Input Invalid
Switching Characteristics
1.6
1.6
1.6
tDSOE SPISS Assertion to Data Out Active
tDSDHI SPISS Deassertion to Data High Impedance
tDDSPID SCK Edge to Data Out Valid (Data Out Delay)
tHDSPID SCK Edge to Data Out Invalid (Data Out Hold)
0
0
10
10
10
0
0
9
0
0
8
ns
ns
ns
ns
9
8
10
10
0
0
0
SPIxSS
(INPUT)
tSDSCI
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SPIxSCK
(INPUT)
tDSOE
tDDSPID
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
CPHA = 1
tSSPID
tHSPID
SPIxMOSI
(INPUT)
tDSOE
tHDSPID
tDDSPID
tDSDHI
SPIxMISO
(OUTPUT)
tHSPID
CPHA = 0
tSSPID
SPIxMOSI
(INPUT)
Figure 28. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. H
| Page 40 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
