ADSP-BF531/ADSP-BF532/ADSP-BF533
Table 31. External Late Frame Sync
VDDEXT = 1.8 V
LQFP/PBGA Packages
VDDEXT = 1.8 V
CSP_BGA Package
VDDEXT = 2.5 V/3.3 V
All Packages
Parameter
Min
Max
Min
Max
Min
Max
Unit
Switching Characteristics
tDDTLFSE Data Delay from Late External TFSx or External RFSx
in multi channel mode with MCMEN = 01, 2
10.5
10.0
10.0
ns
ns
tDTENLFS Data Enable from Late FS or in multi channel mode 0
0
0
with MCMEN = 01, 2
1 In multichannel mode, TFSx enable and TFSx valid follow tDTENLFS and tDDTLFSE
.
2 If external RFSx/TFSx setup to RSCLKx/TSCLK x> tSCLKE/2, then tDDTTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
EXTERNAL RFSx IN MULTI-CHANNEL MODE
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
RSCLKx
RFSx
tDDTLFSE
tDTENLFSE
DTx
1ST BIT
LATE EXTERNAL TFSx
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
TSCLKx
TFSx
tDDTLFSE
DTx
1ST BIT
Figure 26. External Late Frame Sync
Rev. H
| Page 38 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
