ADSP-BF531/ADSP-BF532/ADSP-BF533
Serial Port Timing
Table 28 through Table 31 on Page 38 and Figure 23 on Page 36
through Figure 26 on Page 38 describe Serial Port operations.
Table 28. Serial Ports—External Clock
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx1
3.0
3.0
3.0
3.0
8.0
20.0
3.0
ns
ns
ns
ns
ns
ns
ns
ns
tHFSE TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRE Receive Data Setup Before RSCLKx1
tHDRE Receive Data Hold After RSCLKx1
3.0
3.0
3.0
tSCLKEW TSCLKx/RSCLKx Width
4.5
tSCLKE TSCLKx/RSCLKx Period
15.02
4.0 × tSCLKE
4.0 × tSCLKE
tSUDTE Start-Up Delay From SPORT Enable To First External TFSx3
tSUDRE Start-Up Delay From SPORT Enable To First External RFSx3
Switching Characteristics
4.0 × tSCLKE
4.0 × tSCLKE
tDFSE TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)4
tHOFSE TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1
tDDTE Transmit Data Delay After TSCLKx1
10.0
10.0
10.0
10.0
ns
ns
ns
ns
0.0
0.0
0.0
0.0
tHDTE Transmit Data Hold After TSCLKx1
1 Referenced to sample edge.
2 For receive mode with external RSCLKx and external RFSx only, the maximum specification is 11.11 ns (90 MHz).
3 Verified in design but untested. After being enabled, the serial port requires external clock pulses—before the first external frame sync edge—to initialize the serial port.
4 Referenced to drive edge.
Table 29. Serial Ports—Internal Clock
VDDEXT = 1.8 V
Max
VDDEXT = 2.5 V/3.3 V
Parameter
Min
Min
Max
Unit
Timing Requirements
tSFSI TFSx/RFSx Setup Before TSCLKx/RSCLKx1
tHFSI TFSx/RFSx Hold After TSCLKx/RSCLKx1
tSDRI Receive Data Setup Before RSCLKx1
tHDRI Receive Data Hold After RSCLKx1
Switching Characteristics
11.0
2.0
9.5
9.0
ns
ns
ns
ns
2.0
9.0
0.0
0.0
tDFSI TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
tHOFSI TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)1
tDDTI Transmit Data Delay After TSCLKx1
tHDTI Transmit Data Hold After TSCLKx1
tSCLKIW TSCLKx/RSCLKx Width
3.0
3.0
3.0
3.0
ns
ns
ns
ns
ns
1.0
1.0
2.5
6.0
2.0
4.5
1 Referenced to sample edge.
2 Referenced to drive edge.
Rev. H
| Page 35 of 64 | January 2011
ROCHESTER [ Rochester Electronics ]
