R2025S/D
*1) Pulse Mode:
second
2-Hz and 1-Hz clock pulses are output in synchronization with the increment of the
counter as illustrated in the timing chart below.
CTFG Bit
/INTRA Pin
Approx. 92 s
µ
(Increment of second counter)
Rewriting of the second counter
In the pulse mode, the increment of the second counter is delayed by approximately 92 µs from the
falling edge of clock pulses. Consequently, time readings immediately after the falling edge of clock pulses
may appear to lag behind the time counts of the real-time clocks by approximately 1 second. Rewriting the
second counter will reset the other time counters of less than 1 second, driving the /INTRA pin low.
*2) Level Mode: Periodic interrupt signals are output with selectable interrupt cycle settings of 1 second, 1
minute, 1 hour, and 1 month. The increment of the second counter is synchronized with the falling edge of
periodic interrupt signals. For example, periodic interrupt signals with an interrupt cycle setting of 1 second
are output in synchronization with the increment of the second counter as illustrated in the timing chart below.
CTFG Bit
/INTRA Pin
Setting CTFG bit to 0
Setting CTFG bit to 0
(Increment of
second counter)
(Increment of
second counter)
(Increment of
second counter)
*1), *2) When the oscillation adjustment circuit is used, the interrupt cycle will fluctuate once per 20sec. as
follows:
Pulse Mode:
The “L” period of output pulses will increment or decrement by a maximum of ±3.784ms. For
example, 1-Hz clock pulses will have a duty cycle of 50 ±0.3784%.
Level Mode:
ms.
A periodic interrupt cycle of 1 second will increment or decrement by a maximum of ±3.784
36
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
