R2025S/D
Threshold voltage (2.1V or 1.3V)
VDD
32768Hz Oscillation
Power-on reset flag
(PON)
Oscillation halt
sensing flag (/XST)
VDD supply voltage
monitor flag (VDET)
VDET←0
/XST←1
PON←0
VDET←0
/XST←1
PON←1
VDET←0
/XST←1
PON←0
Internal initialization
period (1 to 2 sec.)
Internal initialization
period (1 to 2 sec.)
When the PON bit is set to 1 in the control register 2, the DEV, F6 to F0, WALE, DALE, /12⋅24, /CLEN2, TEST,
CT2, CT1, CT0, VDSL, VDET, /CLEN1, CTFG, WAFG, and DAFG bits are reset to 0 in the oscillation adjustment
register, the control register 1, and the control register 2. The PON bit is also set to 1 at power-on from 0 volts.
< Considerations in Using Oscillation Halt Sensing Circuit >
Be sure to prevent the oscillation halt sensing circuit from malfunctioning by preventing the following:
1) Instantaneous power-down on the VDD
2) Applying to individual pins voltage exceeding their respective maximum ratings
In particular, note that the /XST bit may fail to be set to 0 in the presence of any applied supply voltage as
illustrated below in such events as backup battery installation. Further, give special considerations to prevent
excessive chattering in the oscillation halt sensing circuit.
VDD
32
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
