欢迎访问ic37.com |
会员登录 免费注册
发布采购

R2025S 参数 Datasheet PDF下载

R2025S图片预览
型号: R2025S
PDF下载: 下载PDF文件 查看货源
内容描述: 高精度I2C总线实时时钟模块 [High precision I2C-Bus Real-Time Clock Module]
分类和应用: 时钟
文件页数/大小: 47 页 / 563 K
品牌: RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
 浏览型号R2025S的Datasheet PDF文件第31页浏览型号R2025S的Datasheet PDF文件第32页浏览型号R2025S的Datasheet PDF文件第33页浏览型号R2025S的Datasheet PDF文件第34页浏览型号R2025S的Datasheet PDF文件第36页浏览型号R2025S的Datasheet PDF文件第37页浏览型号R2025S的Datasheet PDF文件第38页浏览型号R2025S的Datasheet PDF文件第39页  
R2025S/D  
this circuit when set to 1 and to disable it when set to 0. When intended for reading, the flag bits can be used to  
monitor alarm interrupt signals. When intended for writing, the flag bits will cause no event when set to 1 and will  
drive high (disable) the alarm interrupt circuit when set to 0.  
The enable bits will not be affected even when the flag bits are set to 0. In this event, therefore, the alarm  
interrupt circuit will continue to function until it is driven low (enabled) upon the next occurrence of a match between  
current time and preset alarm time.  
The alarm function can be set by presetting desired alarm time in the alarm registers (the Alarm_W Registers for  
the day-of-week digit settings and both the Alarm_W Registers and the Alarm_D Registers for the hour and minute  
digit settings) with the WALE and DALE bits once set to 0 and then to 1 in the Control Register 1. Note that the  
WALE and DALE bits should be once set to 0 in order to disable the alarm interrupt circuit upon the coincidental  
occurrence of a match between current time and preset alarm time in the process of setting the alarm function.  
Interval (1min.) during which a match  
between current time and preset alarm time  
occurs  
/INTRB  
(/INTRA)  
current time =  
current time =  
WALE1  
WALE1  
WALE0  
preset alarm time  
preset alarm time  
(DALE)  
(DALE)  
(DALE)  
/INTRB  
(/INTRA)  
current time =  
preset alarm time  
current time =  
preset alarm time  
WALE1  
(DALE)  
WAFG0  
(DAFG)  
Periodic Interrupt  
Setting of the periodic selection bits (CT2 to CT0) enables periodic interrupt to the CPU. There are two waveform  
modes: pulse mode and level mode. In the pulse mode, the output has a waveform duty cycle of around 50%. In  
the level mode, the output is cyclically driven low and, when the CTFG bit is set to 0, the output is return to High  
(OFF).  
CT2  
CT1  
CT0  
Description  
Wave form  
mode  
Interrupt Cycle and Falling Timing  
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
-
-
OFF(H)  
Fixed at “L”  
2Hz(Duty50%)  
1Hz(Duty50%)  
Once per 1 second (Synchronized with  
Second counter increment)  
Once per 1 minute (at 00 seconds of every  
Minute)  
Once per hour (at 00 minutes and 00  
Seconds of every hour)  
(Default)  
Pulse Mode *1)  
Pulse Mode *1)  
Level Mode *2)  
1
1
1
0
1
1
1
0
1
Level Mode *2)  
Level Mode *2)  
Level Mode *2)  
Once per month (at 00 hours, 00 minutes,  
and 00 seconds of first day of every month)  
35  
 复制成功!