R2025S/D
32-kHz CLOCK OUTPUT
For the R20225S/D, 32.768-kHz clock pulses are output from the 32KOUT pin when the CLKC pin is set to “H”,
and /CLEN1 or /CLEN bit is set to Low. If CLKC is set to low or opened, or /CLEN1 and /CLEN2 are set to high,
the 32KOUT pin is driven low.
/CLEN1 bit
(D3 at Address
Fh)
/CLEN2 bit
(D4 at Address
Eh)
CLKC
pin
32KOUT output pin
(CMOS push-pull
output)
1
1
*
L
*
*
*
0
1
1
0(Default)
*
32kHz clock output
0(Default)
For the R2025S/D, the 32KOUT pin output is synchronized with CLKC pin input as illustrated in the timing chart
below.
CLKC pin
(/CLEN1 or /CLEN2= 0)
32KOUT pin
Max.76.3µs
37
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
