RT5112A
I2C Interface
The following table shows the RT5112Aunique address as below.
RT5112A I2C Slave Address
LSB R/W bit
1/0
MSB
R/W
010000
1
43/42
The I2C interface bus must be connect a resistor 2.2kΩ to power node and independent connection to processor,
individually. The I2C timing diagrams are listed below.
Read and Write Function
Read single byte of data from Register
Slave Address
Register Address
Slave Address
MSB
MSB
Data
LSB
A
A
P
S
0
A
A
A
Sr
Sr
1
A
A
Assume Address = m
Data for Address = m
R/W
Read N bytes of data from Registers
Slave Address
Register Address
Slave Address
MSB
Data 1
LSB
S
0
A
1
Assume Address = m
Data for Address = m
LSB
R/W
MSB
Data 2
LSB
Data N
A
A
P
Data for Address = m + N - 1
LSB
Data for Address = m + 1
Write single byte of data to Register
Slave Address
Register Address
MSB
Data
S
0
A
A
A
A
P
Assume Address = m
Data for Address = m
R/W
Write N bytes of data to Registers
Slave Address
Register Address
MSB
Data 1
LSB MSB
A
Data 2
LSB
S
0
A
A
Assume Address = m
Data for Address = m
MSB
Data for Address = m + 1
LSB
R/W
Data N
A
P
Data for Address = m + N - 1
Driven by Master,
Driven by Slave, P Stop, S Start, Sr Repeat Start
I2C Waveform Information
SDA
t
t
BUF
LOW
t
t
F
t
R
t
F
t
t
R
t
SU;DAT
HD;STA
SP
SCL
t
t
t
SU;STO
HD;STA
SU;STA
t
t
HIGH
HD;DAT
S
P
S
S
r
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32
DS5112A-02 August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
