RT5112A
Addr
RegName
Bit
BitName
Default Type
Description
LDO3 enable. This bit is mask if REG0x03[6:4] :
LDO3_DELAY ≠ 3'b000
0 : Disable (default)
1 : Enable
7
LDO3_EN
0
RW
Note : When LDO3's latch-off protection happen,
this bit will reset to "0"
LDO3 power on/off delay time setting :
000 : Controlled by I2C with REG0x03[7] :
LDO3_EN (default)
001 : SLOT1
010 : SLOT2
011 : SLOT3
RW 100 : SLOT4
101 : SLOT5
LDO3_
DELAY
6:4
000
110 : SLOT6
111 : SLOT7
0x03 LDO3_CTRL
(delay time setting at on/off sequence are reverse)
Note : When LDO3's latch-off protection happen,
these bits will reset to "000"
LDO3 Current limit set bit.
00 : 150mA
RW 01 : 250mA
LDO3_
ILIM
3:2
1:0
11
00
10 : 300mA
11 : 360mA (default)
LDO3 operation mode :
00 : Auto mode (default)
01 : EN forced mode. (High PSRR mode).
RW 10 : Bypass mode. LDO3 internal power MOSFET
turns on fully.
LDO3_
MODE
11 : Bypass mode. LDO3 internal power MOSFET
turns on fully.
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is a registered trademark of Richtek Technology Corporation.
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36
DS5112A-02 August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
