RT5112A
Interrupt
Fault Event and Status
The RT5112Ainterrupt controller continuously monitors the device operation. Once the fault is ever detected, the fault
event bit will be set to 1 and the open drain interrupt indicate pin INTRB will be driven to ground level. Meanwhile, the
fault status bit will also be set to 1 to show the present fault. When the host reads the fault event bit and set interrupt
clear bit 0x14[0] = 1, the INTRB pin will be released to high impedance. The fault status bit goes back to 0 only till the
fault condition is cleared.
Table 3. Interrupt
Fault Event
BUCK_UV_EVT 0x15[7]
LDO1_UV_EVT 0x15[6]
LDO2_UV_EVT 0x15[5]
LDO3_UV_EVT 0x15[4]
LDO4_UV_EVT 0x15[3]
BUCK2_UV_EVT 0x15[1]
BUCK_OV_EVT 0x16[7]
LDO1_OV_EVT 0x16[6]
LDO2_OV_EVT 0x16[5]
LDO3_OV_EVT 0x16[4]
LDO4_OV_EVT 0x16[3]
BUCK2_OV_EVT 0x16[1]
BUCK_OCP_EVT 0x17[7]
LDO1_OCP_EVT 0x17[6]
LDO2_OCP_EVT 0x17[5]
LDO3_OCP_EVT 0x17[4]
LDO4_OCP_EVT 0x17[3]
BUCK2_OCP_EVT 0x17[1]
TWARN_EVT 0x19[7]
Fault Status
BUCK_UV_STAT 0x2B[7]
LDO1_UV_STAT 0x2B[6]
LDO2_UV_STAT 0x2B[5]
LDO3_UV_STAT 0x2B[4]
LDO4_UV_STAT 0x2B[3]
BUCK2_UV_STAR 0x2B[1]
BUCK_OV_STAT 0x2C[7]
LDO1_OV_STAT 0x2C[6]
LDO2_OV_STAT 0x2C[5]
LDO3_OV_STAT 0x2C[4]
LDO4_OV_STAT 0x2C[3]
BUCK2_OV_STAT 0x2C[1]
BUCK_OCP_STAT 0x2D[7]
LDO1_OCP_STAT 0x2D[6]
LDO2_OCP_STAT 0x2D[5]
LDO3_OCP_STAT 0x2D[4]
LDO4_OCP_STAT 0x2D[3]
BUCK2_OCP_STAT 0x2D[1]
TWARN_STAT 0x2F[7]
Description
BUCK output under-voltage
LDO1 output under-voltage
LDO2 output under-voltage
LDO3 output under-voltage
LDO4 output under-voltage
BUCK2 output under-voltage
BUCK output over-voltage
LDO1 output over-voltage
LDO2 output over-voltage
LDO3 output over-voltage
LDO4 output over-voltage
BUCK2 output over-voltage
BUCK over-current
LDO1 over-current
LDO2 over-current
LDO3 over-current
LDO4 over-current
BUCK2 over-current
Thermal warning
TSD_EVT 0x19[6]
TSD_STAT 0x2F[6]
Thermal shutdown
VSYSUV_EVT 0x19[5]
VSYSOV_EVT 0x19[4]
VSYSUV_STAT 0x2F[5]
VSYSOV_STAT 0x2B[4]
System under-voltage
System over-voltage
Fault Event Mask
The host can set the fault event mask bits to hide the fault events. When the mask bit is set to 1, the corresponding
fault is hidden and the interrupt indicate pin INTRB will keep high impedance without being pulled to ground level. The
host requires to read the fault event bits to clear its value to 0, otherwise the interrupt indicate pin INTRB will be driven
to low level again when mask bits being set to 1. The mask bits will be reset to default value with conditions : HWEN
voltage goes to low level or IC power shutdown.
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30
DS5112A-02 August 2019
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
