RT5112A
I2C Register Table
R : Read only.
RC : Read then Clear.
RW : Read and Wirte.
WC : Write “1” then clear to “0” after this procedure finish.
Note 6. Below registers setting are only available on the RT5112.
0x05, 0x08, 0x0A[5][0], 0x0B[5][1], 0x11[7:2], 0x13[1:0], 0x14[3:2], 0x15[2][0], 0x16[2], 0x17[2], 0x2B[2][0], 0x2C[2],
0x2D[2], 0x30[2], 0x32[2][0], 0x33[2], 0x34[2], 0x37[5][3:2], 0x3B[2] and 0x43[7:6].
Addr
RegName
Bit
BitName
Default Type
Description
Buck enable. This bit is mask if REG0x00[6:4] :
BUCK_DELAY ≠ 3'b000
0 : Disable (default)
7
BUCK_EN
0
RW
1 : Enable
Note : When Buck's latch-off protection happen,
this bit will reset to "0"
Buck power on/off delay time setting:
000 : Controlled by I2C with REG0x00[7] :
BUCK_EN (default)
001 : SLOT1
010 : SLOT2
011 : SLOT3
100 : SLOT4
101 : SLOT5
BUCK_
DELAY
6:4
000
RW
110 : SLOT6
111 : SLOT7
0x00 Buck_CTRL
(delay time setting at on/off sequence are reverse)
Note : When Buck's latch-off protection happen,
these bits will reset to "000"
Buck current limit set bit.
00 : 1.5A
01 : 2A (default)
10 : 2.5A
BUCK_
ILIM
3:2
1:0
01
00
RW
RW
11 : 3A
Buck operation mode :
00 : Auto PFM mode (default)
01 : Forced PWM mode
10 : Ultra sonic mode
11 : Normal mode
BUCK_
MODE
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©
is a registered trademark of Richtek Technology Corporation.
DS5112A-02 August 2019
www.richtek.com
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