Ovr_39 → 0xB9B9
Ovr_4F → 0XCF66
Ovr_77 → 0XF75C
5. For the remote TRC104, write the following additional configuration constants to the radio, cycling the
CS control line to 0 for at least 5 µs between each write:
TX_Pwr → 0X811B
FIFO_Sz → 0X8503
Pre_Ctl → 0X86B0
Addr_len → 0X8802
Rm_Snd_Lo → 0X8E02
Rm_Snd_Hi → 0X8FAA
Rm_Dst_Lo → 0X8901
Rm_Dst_Hi → 0X8AAA
PLL_Del → 0X9401
Ovr_2C → 0XAC18
Ovr_39 → 0xB9B9
Ovr_4F → 0XCF66
Ovr_77 → 0XF75C
6. Enter Standby Mode by setting control line PMODE to 1, and control lines CS and MODE to 0. This
mode, Stop Mode, Configuration Mode, Transmit Load/Receive Mode or Burst Transmit Mode can
be used without re-initialization. Re-initialization is always required following Sleep Mode or Power-up.
9.2 Burst Packet Transmission
1. To transmit, enter Configuration Mode by setting control line MODE to 0, and control lines CS
and PMODE to 1.
2. Write the Ch_8_TX configuration register constant 0X8088 to the TRC104. Then set the CS control
line to 0 for at least 5 µs.
3. With CS still 0, set control lines PMODE and MODE to 1 to enter Transmit Load/Receive Mode.
4. The host microcontroller will clock the transmit bits into of the FIFO.
5. After a 20 µs delay, begin clocking transmit bits into the FIFO, loading the four payload data bytes.
6. Count each bit input to the transmit FIFO until the FIFO is completely filled (4 bytes = 32 bits).
7. Then add three additional clock cycles. The bits on these three clock cycles can be any value.
Internally the radio replaces the placeholder bytes with the destination and sender addresses.
8. Set the MODE control line to 0. This initiates the RF transmission.
9. The INT flag is asserted when the RF transmission is complete.
10. Placing the TRC104 in another operating mode, such as Transmit Load/Receive Mode, will
reset the INT flag.
9.3 Burst Packet Reception
1. To receive, enter Configuration Mode by setting control line MODE to 0, and lines CS and PMODE to 1.
2. Write the Ch_8_RX configuration register constant 0X8008 to the TRC104. Then set the CS control
line to 0 for at least 5 µs.
3. With CS still 0, set control lines PMODE and MODE to 1 to enter Transmit Load/Receive Mode.
4. In receive, the INT flag is asserted to indicate there are received bits in the FIFO.
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Page 31 of 33
TRC104 - 08/13/09
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