9 Configuration Example
This example details the configuration of a TRC104 application with the following specifications:
Radios in System
Base and remote
2408 MHz, 0 dBm
1 Mb/s
Operating Frequency and Power
RF Data Rate
Address Length
2 bytes
Base Address
0XAA01
Remote Address
0XAA02
Destination Address
Auto-insert
Enabled, auto-insert
Enabled
Sender Address Option
Sender Address Output on Receive
Payload Data Length
DC-Balanced Data Scrambling
CRC Error Detection
4 bytes
Enabled
Enabled
Packet Error Handling
PLL Pre-start
Discard
Enabled
Power Amplifier Ramp Up/Down Timing
INT Flag Assertion State
Host Serial Clocking Rate
10/5 µs
High
1 Mb/s
9.1 Burst Packet Mode Initialization
The following table of 16-bit register configuration constants are used to initialize and control the radios. The most
significant bit of the first byte is the configuration write bit. The next seven bits specify the register address. The
second byte specifies the register configuration.
Label
Ch_8_RX
Hex Constant
0X8008
Configuration Register Detail
T/R and Channel Control 0X00: RX, 2408 MHz
Ch_8_TX
TX_Pwr
0X8088
T/R and Channel Control 0X00: TX, 2408 MHz
0x811B
TX Power and Crystal Frequency Control 0X01: 0 dBm, 16 MHz
Data Format Control 0x05: auto-insert destination in TX, auto-insert sender in TX, output
sender with RX, 4 byte FIFO
FIFO_Sz
0X8503
Pre_Ctl
0x86B0
0X8802
0X8E01
0X8FAA
0X8902
0X8AAA
0X8E02
0X8FAA
0X8901
0X8AAA
0X9401
0XAC18
0XB9B9
0XCF66
0XF75C
Preamble Control 0X06: default override for enhanced performance
Address Length Control 0X08: 2-byte addressing
Addr_Len
Bs_Snd_Lo
Bs_Snd_Hi
Bs_Dst_Lo
Bs_Dst_Hi
Rm_Snd_Lo
Rm_Snd_Hi
Rm_Dst_Lo
Rm_Dst_Hi
PLL_Del
Base Sender (Local Device) Low Address 0X0E: base low address byte
Base Sender (Local Device) High Address 0X0F: base high address byte
Base Destination Low Address 0X09: remote low address byte
Base Destination High Address 0X0A: remote high address byte
Remote Sender (Local Device) Low Address 0X0E: remote low address byte
Remote Sender (Local Device) High Address 0X0F: remote high address byte
Remote Destination Low Address 0X09: base low address byte
Remote Destination High Address 0X0A: base high address byte
PLL Turn-on Control Address 0X14: 20 µs delay
Ovr_2C
Register 0x2C: default override for enhanced performance
Register 0x39: default override for enhanced performance
Register 0x4F: default override for enhanced performance
Register 0x77: default override for enhanced performance
Ovr_39
Ovr_4F
Ovr_77
Table 39
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TRC104 - 08/13/09
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