8.3 Data Function Control
0x02 [default 0x78]
Address
Name
Bits
R/W
Description
-
7
r/w
Reserved, always set to 0b
Data Mode Select:
0 → Continuous Mode
1 → Burst Mode
D_Mode
DR
6
5
r/w
r/w
Data Rate Select:
0 → 250 kb/s
1 →1 Mb/s
DC-balanced Data Scrambling Enable bit (Burst Mode only):
0 → Disable Data Scrambling
Ciph_En
CRC_En
4
3
r/w
r/w
0X02
1 → Enable Data Scrambling
Scramble Polynomial = X7 + X4 + 1
CRC-16 Enable bit (Burst Mode only):
0 → Disable CRC
1 → Enable CRC
CRC Polynomial = X16 + X12 + X5 + 1
2..1
0
r/w
r/w
Reserved, always set to 0b
Controls clearing the FIFO in Burst Receive Mode if the CRC fails for the current packet
0 → Discard on CRC error
CRC_ERR
1 → Do not discard on CRC error
Table 18
8.4 RSSI Function Control
0x03 [default 0x87]
Address
Name
Bits
R/W
Description
-
7..5
r/w
Reserved, always set to 000b
Analog RSSI refresh control bit (Continuous Mode only):
0 → Do not refresh RSSI value
RSSIA_Rfsh
RSSIA_thr
4
r/w
r/w
0X03
1 → Refresh RSSI value
See Section 3.7 for details of RSSI operation
DRSSI threshold: when the RSSIA level exceeds RSSIA_thr, the RSSID pin is set high
3..0
default is 0111b
Table 19
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Page 23 of 33
TRC104 - 08/13/09
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