Item Description
Min Typ Max Unit
T1
T2
T3
T4
T5
T6
CS to 1st Bit Time
20
200
10
µs
ns
ns
ns
ns
ns
SCLK Cycle Time
Setup Time
Hold Time
10
Data Bit Hold Time
Last Bit to CS Time
20
50
Table 14
Figure 20 and Table 5 show the timing for a configuration write sequence to the TRC104.
C
o
n
f
i
g
u
r
a
t
i
o
n
B
y
t
e
W
r
i
t
e
T
i
m
i
n
g
C
S
S
T
1
R
/
W
D
C
A
L
T
A
6
A
5
A
1
A
0
D
7
D
6
D
5
D
1
D
0
S
K
T
2
T
3
T
4
T
5
Figure 20
Item Description
Min Typ Max Unit
T1
T2
T3
T4
T5
CS to 1st bit time
SCLK cycle time
Setup time
20
200
10
µs
ns
ns
ns
ns
Hold time
10
Last bit to CS time
50
Table 15
7.2 Transmit/Receive FIFO Access
Serial data is sent or received through the FIFO according to the TRC104 mode of operation. If the TRC104 is
configured for Burst Receive Mode, a FIFO read transaction is implemented on the serial interface. If the TRC104
is configured for Burst Transmit Mode, a FIFO write transaction is implemented on the serial interface. The CS pin
must be held low during FIFO transactions. If the CS is allowed to go high, the TRC104 will interpret the data as a
register configuration transaction and possibly corrupt the device configuration. See Sections 5.2.1 and 5.2.2 for
details on Burst Transmit Mode and Burst Receive Mode using the FIFO.
8 Configuration Registers
The TRC104’s user configuration registers are mapped in the address range of 0x00 through 0x18. Sections 8.1
through 8.17 below provide the details for each configuration register. Power-up default settings for the
configuration register bit and byte patterns are shown in bold.
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TRC104 - 08/13/09
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