6.4 DC-Balanced Scrambling
The TRC104 is equipped with a scrambling/descrambling function to improve the DC-balance of a transmitted bit
stream. The implementation is show in Figure 16. This function is enabled by setting the SCR_En bit in
configuration register 0x02 to 1. The scrambling/descramble function is only available in Burst Packet Mode.
T
R
C
1
0
4
D
a
t
a
S
c
r
a
m
b
l
i
n
g
I
m
p
l
e
m
e
n
t
a
t
i
o
n
7
4
X
+
X
+
1
X
O
R
S
D
C R A M B L E D
T A O U T P U T
S
R
6
S
R
4
S
R
3
S
R
0
X
O
R
A
D
A
T
A
I
N
P
U
T
A
l
l
7
s
h
i
f
t
r
e
g
i
s
t
e
r
s
s
e
t
t
o
1
b
e
f
o
r
e
e
a
c
h
s
c
r
a
m
b
l
i
n
g
(
D
C
b
a
l
a
n
c
i
n
g
)
c
a
l
c
u
l
a
t
i
o
n
Figure 16
6.4 CRC Error Detection
The CRC error detection option is enabled by setting the CRC_En bit in configuration register 0x02 to 1. A two-
byte CRC is automatically calculated on the payload field and appended to the end of the transmitted packet. On
the receive side, the CRC is recalculated on the payload field and compared to the received CRC. If the CRC
match fails, the received packet is handled according to the setting of the CRC_ERR bit in configuration register
0x02. Otherwise, a good CRC match generates a flag on the INT pin, and the received CRC is discarded. The
polarity of the INT flag is configured by the LVLINT bit in configuration register 0x17. There is no interrupt
generation for a failed packet. The CRC calculation is based on the CCITT polynomial as shown in Figure 17.
T
R C 1 0 4 C R C I m p l e m e n t a t i o n
2
1
6
1
5
X
+
X
+
X
+
1
D A T A
I N P U T
S
R
1
2
X
O
R
S
R
1
1
X
O
R
S
R
0
X
O
R
S
R
1
5
S
R
5
S
R
4
A
l
l
1
6
s
h
i
f
t
r
e
g
i
s
t
e
r
s
s
e
t
t
o
1
b
e
f
o
r
e
e
a
c
h
C
R
C
c
a
l
c
u
l
a
t
i
o
n
Figure 17
7 Serial Interface
The serial interface provides two-wire serial communication between the TRC104 and its host microcontroller, as
shown in Figure 18. All FIFO and configuration parameters are accessible through the serial interface. The FIFO
and configuration data pass through the bidirectional SDAT pin with host microcontroller clocking on the SCLK
pin. The CS pin state selects whether the FIFO (Burst Packet Mode only) or the internal configuration registers
are accessed.
www.RFM.com E-mail: info@rfm.com
©2009 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 19 of 33
TRC104 - 08/13/09
RFM [ RF MONOLITHICS, INC ]
