RX62N Group, RX621 Group
4. I/O Registers
Table 4.1
List of I/O Registers (Address Order) (28 / 35)
Module
Register
Number Access
Number of
Address
Abbreviation Register Name
Abbreviation of Bits
Size
Access Cycles
0008 C2AFh
0008 C400h
0008 C402h
0008 C404h
0008 C406h
0008 C408h
0008 C40Ah
0008 C40Ch
0008 C40Eh
0008 C410h
0008 C412h
0008 C414h
0008 C416h
0008 C418h
0008 C41Ah
0008 C41Ch
0008 C41Eh
0008 C422h
0008 C424h
SYSTEM
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
RTC
Deep standby backup register 31
DPSBKR31
R64CNT
RSECCNT
RMINCNT
RHRCNT
RWKCNT
RDAYCNT
RMONCNT
RYRCNT
RSECAR
RMINAR
RHRAR
8
8
4 to 5 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
64-Hz counter
8
8
Second counter
8
8
Minute counter
8
8
Hour counter
8
8
Day-of-week counter
Date counter
8
8
8
8
Month counter
8
8
Year counter
16
8
16
Second alarm register
Minute alarm register
Hour alarm register
Day-of-week alarm register
Date alarm register
Month alarm register
Year alarm register
Year alarm enable register
RTC control register 1
RTC control register 2
Mailbox registers 0 to 31
8
8
8
8
8
RWKAR
8
8
RDAYAR
RMONAR
RYRAR
8
8
8
8
16
8
16
RYRAREN
RCR1
8
8
8
RCR2
8
8
0009 0200h to CAN0
0009 03FFh
MB0 to
MB031
128
8, 16, 32
0009 0400h
0009 0404h
0009 0408h
0009 040Ch
0009 0410h
0009 0414h
0009 0418h
0009 041Ch
0009 0420h
0009 0424h
0009 0428h
0009 042Ch
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Mask register 0
MKR0
MKR1
MKR2
MKR3
MKR4
MKR5
MKR6
MKR7
FIDCR0
FIDCR1
MKIVLR
MIER
32
32
32
32
32
32
32
32
32
32
32
32
8
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
Mask register 1
Mask register 2
Mask register 3
Mask register 4
Mask register 5
Mask register 6
Mask register 7
FIFO received ID compare register 0
FIFO received ID compare register 1
Mask invalid register
Mailbox interrupt enable register
Message control registers 0 to 31
0009 0820h to CAN0
0009 083Fh
C0MCTL0 to
C0MCTL031
0009 0840h
0009 0842h
0009 0844h
0009 0848h
0009 0849h
0009 084Ah
0009 084Bh
0009 084Ch
0009 084Dh
0009 084Eh
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
CAN0
Control register
CTLR
STR
16
16
32
8
8, 16
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
2 to 3 PCLK*8
Status register
8, 16
Bit configuration register
BCR
8, 16, 32
Receive FIFO control register
Receive FIFO pointer control register
Transmit FIFO control register
Transmit FIFO pointer control register
Error interrupt enable register
Error interrupt factor judge register
Receive error count register
RFCR
RFPCR
TFCR
TFPCR
EIER
8
8
8
8
8
8
8
8
8
8
8
EIFR
8
RECR
8
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
Page 79 of 146
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