RX62N Group, RX621 Group
4. I/O Registers
4.
I/O Registers
Table 4.1
List of I/O Registers (Address Order) (1 / 35)
Module
Register
Number Access
Number of
Address
Abbreviation Register Name
Abbreviation of Bits
Size
16
16
16
16
16
32
32
32
32
8
Access Cycles
0008 0000h
0008 0002h
0008 0006h
0008 0008h
0008 000Ch
0008 0010h
0008 0014h
0008 0018h
0008 0020h
0008 0030h
0008 0040h
0008 1300h
0008 1304h
0008 1308h
0008 130Ah
0008 2000h
0008 2004h
0008 2008h
0008 200Ch
0008 2010h
0008 2013h
0008 2014h
0008 2018h
0008 201Ch
0008 201Dh
0008 201Eh
0008 201Fh
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
SYSTEM
BSC
Mode monitor register
MDMONR
MDSR
16
16
16
16
16
32
32
32
32
8
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
3 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
Mode status register
System control register 0
System control register 1
Standby control register
SYSCR0
SYSCR1
SBYCR
Module stop control register A
Module stop control register B
Module stop control register C
System clock control register
External bus clock control register
MSTPCRA
MSTPCRB
MSTPCRC
SCKCR
BCKCR
Oscillation stop detection control register OSTDCR
16
8
16
8
Bus error status clear register
Bus error monitoring enable register
Bus error status register 1
Bus error status register 2
DMA source address register
DMA destination address register
DMA transfer count register
DMA block transfer count register
DMA transfer mode register
DMA interrupt setting register
DMA address mode register
DMA offset register
BERCLR
BEREN
BERSR1
BERSR2
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
BSC
8
8
BSC
8
8
BSC
16
32
32
32
16
16
8
16
32
32
32
16
16
8
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAC0
DMAMD
DMOFR
DMCNT
DMREQ
DMSTS
DMCSL
16
32
8
16
32
8
MA transfer enable register
DMA software start register
DMA status register
8
8
8
8
DMA activation source flag control
register
8
8
0008 2040h
0008 2044h
0008 2048h
0008 204Ch
0008 2050h
0008 2053h
0008 2054h
0008 205Ch
0008 205Dh
0008 205Eh
0008 205Fh
DMAC1
DMAC1
DMAC1
DMAC1
DMAC1
DMAC1
DMAC1
DMAC1
DMAC1
DMAC1
DMAC1
DMA source address register
DMA destination address register
DMA transfer count register
DMA block transfer count register
DMA transfer mode register
DMA interrupt setting register
DMA address mode register
MA transfer enable register
DMA software start register
DMA status register
DMSAR
DMDAR
DMCRA
DMCRB
DMTMD
DMINT
32
32
32
16
16
8
32
32
32
16
16
8
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
2 ICLK
DMAMD
DMCNT
DMREQ
DMSTS
DMCSL
16
8
16
8
8
8
8
8
DMA activation source flag control
register
8
8
0008 2080h
0008 2084h
0008 2088h
DMAC2
DMAC2
DMAC2
DMA source address register
DMA destination address register
DMA transfer count register
DMSAR
DMDAR
DMCRA
32
32
32
32
32
32
2 ICLK
2 ICLK
2 ICLK
R01DS0052EJ0110 Rev.1.10
Feb 10, 2011
Page 52 of 146