R8C/13 Group
6. Clock Generating Circuit
High-speed on-chip oscillator control register 1 (7-bit)
Frequency adjustable
f
RING-fast
On-chip
oscillator
clock
High-speed
on-chip
oscillator
HR00
HR01=1
HR01=0
f
RING
f
RING128
1/128
Low-speed
on-chip
oscillator
CM14
fRING-S
Voltage
f
1
f
1SIO
detection
circuit
f
AD
f
2
Peripheral
function clock
Oscillation
stop
f
8
detection
f
f
8SIO
OCD2=1
f
32
Main
clock
e
c
32SIO
b
CM10=1(Stop mode)
S
R
Q
a
d
Divider
CPU clock
X
OUT
OCD2=0
XIN
RESET
Hardware reset2
CM13
Power on reset
Interrupt request level
judgment output
CM05
Voltage detective
interrupt
CM02
S
R
Q
WAIT instruction
R
c
e
b
1/2
1/2
1/2
1/2
1/2
a
CM06=0
CM17 to CM16=11
2
CM06=1
CM06=0
CM17 to CM16=10
d
2
CM06=0
CM17 to CM16=01
2
CM06=0
CM17 to CM16=00
2
CM02, CM05, CM06: Bits in CM0 register
CM10, CM13, CM14, CM16, CM17: Bits in CM1 register
OCD0, OCD1, OCD2: Bits in OCD register
HR00, HR01: Bits in HR0 register
Details of divider
Oscillation stop detection circuit
(1)
Forcible discharge when OCD0 =0
Pulse generation
circuit for clock
edge detection
and charge,
discharge control
circuit
Charge,
discharge
circuit
Oscillation stop
detection interrupt
generation circuit
Main clock
Oscillation stop
detection,
Watchdog timer,
Voltage
(1)
OCD1
Watchdog
timer
interrupt
detection
interrupt
OCD2 bit switch signal
CM14 bit switch signal
NOTES:
1. Set the same value to the OCD1 bit and OCD0 bit.
Figure 6.1 Clock Generation Circuit
Rev.1.20 Jan 27, 2006 page 30 of 205
REJ09B0111-0120
RENESAS [ RENESAS TECHNOLOGY CORP ]
